/*
 *Copyright (c) 2024 Black Sesame Technologies
 *
 *Licensed under the Apache License, Version 2.0 (the "License");
 *you may not use this file except in compliance with the License.
 *You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 *Unless required by applicable law or agreed to in writing, software
 *distributed under the License is distributed on an "AS IS" BASIS,
 *WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *See the License for the specific language governing permissions and
 *limitations under the License.
*/
#ifndef SWT_LSP_CRM_REG_TABLE_H
#define SWT_LSP_CRM_REG_TABLE_H
#define SWT_LSP_CRM_REG_CTRL_BASE_ADDR		(0X217A0000UL)

#define LOCAL_RST_CFG_OFFSET                 (0x00U)
#define CLK_GATE_CFG_OFFSET                  (0x04U)
#define PARITY_CFG_OFFSET                    (0x08U)
#define LSP_SFT_CFG_CTRL_OFFSET              (0x0cU)
#define TIMER_SFT_CFG_CTRL_OFFSET            (0x10U)
#define CAN_SFT_CFG_CTRL_OFFSET              (0x14U)
#define CAN0_IP_CFG_OFFSET                   (0x18U)
#define CAN1_IP_CFG_OFFSET                   (0x1cU)
#define CAN2_IP_CFG_OFFSET                   (0x20U)
#define CAN3_IP_CFG_OFFSET                   (0x24U)
#define CAN4_IP_CFG_OFFSET                   (0x28U)
#define CAN5_IP_CFG_OFFSET                   (0x2cU)
#define CAN6_IP_CFG_OFFSET                   (0x30U)
#define CAN7_IP_CFG_OFFSET                   (0x34U)
#define CAN8_IP_CFG_OFFSET                   (0x38U)
#define CAN9_IP_CFG_OFFSET                   (0x3cU)
#define CAN10_IP_CFG_OFFSET                  (0x40U)
#define CAN11_IP_CFG_OFFSET                  (0x44U)
#define CAN12_IP_CFG_OFFSET                  (0x48U)
#define CAN13_IP_CFG_OFFSET                  (0x4cU)
#define CAN14_IP_CFG_OFFSET                  (0x50U)
#define CAN15_IP_CFG_OFFSET                  (0x54U)
#define CAN0_SR_CFG_OFFSET                   (0x58U)
#define CAN1_SR_CFG_OFFSET                   (0x5cU)
#define CAN2_SR_CFG_OFFSET                   (0x60U)
#define CAN3_SR_CFG_OFFSET                   (0x64U)
#define CAN4_SR_CFG_OFFSET                   (0x68U)
#define CAN5_SR_CFG_OFFSET                   (0x6cU)
#define CAN6_SR_CFG_OFFSET                   (0x70U)
#define CAN7_SR_CFG_OFFSET                   (0x74U)
#define CAN8_SR_CFG_OFFSET                   (0x78U)
#define CAN9_SR_CFG_OFFSET                   (0x7cU)
#define CAN10_SR_CFG_OFFSET                  (0x80U)
#define CAN11_SR_CFG_OFFSET                  (0x84U)
#define CAN12_SR_CFG_OFFSET                  (0x88U)
#define CAN13_SR_CFG_OFFSET                  (0x8cU)
#define CAN14_SR_CFG_OFFSET                  (0x90U)
#define CAN15_SR_CFG_OFFSET                  (0x94U)
#define LSP_DEBUG_SEL_OFFSET                 (0x98U)
#define CANFD_CTRL_OFFSET                    (0x9cU)
#define CANFD_TIMESTAMP_VALUE_H_OFFSET       (0xa0U)
#define CANFD_TIMESTAMP_VALUE_L_OFFSET       (0xa4U)
#define CANFD_TIMESTAMP_COUNTER_OFFSET       (0xa8U)
#define LSP_FREQ_CHECK_EN_OFFSET             (0xacU)
#define LSP_RREQ_INTR0_OFFSET                (0xb0U)
#define LSP_RREQ_INTR1_OFFSET                (0xb4U)
#define LSP_RREQ_INTR2_OFFSET                (0xb8U)
#define LSP_WCLK_RREQ_REF_CLKCNT_OFFSET      (0xbcU)
#define LSP_WCLK_RREQ_HIGHCLKCNT_OFFSET      (0xc0U)
#define LSP_WCLK_RREQ_THRESHOLD_OFFSET       (0xc4U)
#define LSP_WCLK_RREQ_HIGHCLK_PPM_OFFSET     (0xc8U)
#define LSP_PCLK_RREQ_REF_CLKCNT_OFFSET      (0xccU)
#define LSP_PCLK_RREQ_HIGHCLKCNT_OFFSET      (0xd0U)
#define LSP_PCLK_RREQ_THRESHOLD_OFFSET       (0xd4U)
#define LSP_PCLK_RREQ_HIGHCLK_PPM_OFFSET     (0xd8U)
#define RAY_WCLK_RREQ_REF_CLKCNT_OFFSET      (0xdcU)
#define RAY_WCLK_RREQ_HIGHCLKCNT_OFFSET      (0xe0U)
#define RAY_WCLK_RREQ_THRESHOLD_OFFSET       (0xe4U)
#define RAY_WCLK_RREQ_HIGHCLK_PPM_OFFSET     (0xe8U)
#define LIN_WCLK_RREQ_REF_CLKCNT_OFFSET      (0xecU)
#define LIN_WCLK_RREQ_HIGHCLKCNT_OFFSET      (0xf0U)
#define LIN_WCLK_RREQ_THRESHOLD_OFFSET       (0xf4U)
#define LIN_WCLK_RREQ_HIGHCLK_PPM_OFFSET     (0xf8U)
#define LIN_PCLK_RREQ_REF_CLKCNT_OFFSET      (0xfcU)
#define LIN_PCLK_RREQ_HIGHCLKCNT_OFFSET      (0x100U)
#define LIN_PCLK_RREQ_THRESHOLD_OFFSET       (0x104U)
#define LIN_PCLK_RREQ_HIGHCLK_PPM_OFFSET     (0x108U)
#define CAN0_CLK_RREQ_REF_CLKCNT_OFFSET      (0x10cU)
#define CAN0_CLK_RREQ_HIGHCLKCNT_OFFSET      (0x110U)
#define CAN0_CLK_RREQ_THRESHOLD_OFFSET       (0x114U)
#define CAN0_CLK_RREQ_HIGHCLK_PPM_OFFSET     (0x118U)
#define CAN1_CLK_RREQ_REF_CLKCNT_OFFSET      (0x11cU)
#define CAN1_CLK_RREQ_HIGHCLKCNT_OFFSET      (0x120U)
#define CAN1_CLK_RREQ_THRESHOLD_OFFSET       (0x124U)
#define CAN1_CLK_RREQ_HIGHCLK_PPM_OFFSET     (0x128U)
#define CAN2_CLK_RREQ_REF_CLKCNT_OFFSET      (0x12cU)
#define CAN2_CLK_RREQ_HIGHCLKCNT_OFFSET      (0x130U)
#define CAN2_CLK_RREQ_THRESHOLD_OFFSET       (0x134U)
#define CAN2_CLK_RREQ_HIGHCLK_PPM_OFFSET     (0x138U)
#define CAN3_CLK_RREQ_REF_CLKCNT_OFFSET      (0x13cU)
#define CAN3_CLK_RREQ_HIGHCLKCNT_OFFSET      (0x140U)
#define CAN3_CLK_RREQ_THRESHOLD_OFFSET       (0x144U)
#define CAN3_CLK_RREQ_HIGHCLK_PPM_OFFSET     (0x148U)
#define CAN4_CLK_RREQ_REF_CLKCNT_OFFSET      (0x14cU)
#define CAN4_CLK_RREQ_HIGHCLKCNT_OFFSET      (0x150U)
#define CAN4_CLK_RREQ_THRESHOLD_OFFSET       (0x154U)
#define CAN4_CLK_RREQ_HIGHCLK_PPM_OFFSET     (0x158U)
#define CAN5_CLK_RREQ_REF_CLKCNT_OFFSET      (0x15cU)
#define CAN5_CLK_RREQ_HIGHCLKCNT_OFFSET      (0x160U)
#define CAN5_CLK_RREQ_THRESHOLD_OFFSET       (0x164U)
#define CAN5_CLK_RREQ_HIGHCLK_PPM_OFFSET     (0x168U)
#define CAN6_CLK_RREQ_REF_CLKCNT_OFFSET      (0x16cU)
#define CAN6_CLK_RREQ_HIGHCLKCNT_OFFSET      (0x170U)
#define CAN6_CLK_RREQ_THRESHOLD_OFFSET       (0x174U)
#define CAN6_CLK_RREQ_HIGHCLK_PPM_OFFSET     (0x178U)
#define CAN7_CLK_RREQ_REF_CLKCNT_OFFSET      (0x17cU)
#define CAN7_CLK_RREQ_HIGHCLKCNT_OFFSET      (0x180U)
#define CAN7_CLK_RREQ_THRESHOLD_OFFSET       (0x184U)
#define CAN7_CLK_RREQ_HIGHCLK_PPM_OFFSET     (0x188U)
#define CAN8_CLK_RREQ_REF_CLKCNT_OFFSET      (0x18cU)
#define CAN8_CLK_RREQ_HIGHCLKCNT_OFFSET      (0x190U)
#define CAN8_CLK_RREQ_THRESHOLD_OFFSET       (0x194U)
#define CAN8_CLK_RREQ_HIGHCLK_PPM_OFFSET     (0x198U)
#define CAN9_CLK_RREQ_REF_CLKCNT_OFFSET      (0x19cU)
#define CAN9_CLK_RREQ_HIGHCLKCNT_OFFSET      (0x1a0U)
#define CAN9_CLK_RREQ_THRESHOLD_OFFSET       (0x1a4U)
#define CAN9_CLK_RREQ_HIGHCLK_PPM_OFFSET     (0x1a8U)
#define CAN10_CLK_RREQ_REF_CLKCNT_OFFSET     (0x1acU)
#define CAN10_CLK_RREQ_HIGHCLKCNT_OFFSET     (0x1b0U)
#define CAN10_CLK_RREQ_THRESHOLD_OFFSET      (0x1b4U)
#define CAN10_CLK_RREQ_HIGHCLK_PPM_OFFSET    (0x1b8U)
#define CAN11_CLK_RREQ_REF_CLKCNT_OFFSET     (0x1bcU)
#define CAN11_CLK_RREQ_HIGHCLKCNT_OFFSET     (0x1c0U)
#define CAN11_CLK_RREQ_THRESHOLD_OFFSET      (0x1c4U)
#define CAN11_CLK_RREQ_HIGHCLK_PPM_OFFSET    (0x1c8U)
#define CAN12_CLK_RREQ_REF_CLKCNT_OFFSET     (0x1ccU)
#define CAN12_CLK_RREQ_HIGHCLKCNT_OFFSET     (0x1d0U)
#define CAN12_CLK_RREQ_THRESHOLD_OFFSET      (0x1d4U)
#define CAN12_CLK_RREQ_HIGHCLK_PPM_OFFSET    (0x1d8U)
#define CAN13_CLK_RREQ_REF_CLKCNT_OFFSET     (0x1dcU)
#define CAN13_CLK_RREQ_HIGHCLKCNT_OFFSET     (0x1e0U)
#define CAN13_CLK_RREQ_THRESHOLD_OFFSET      (0x1e4U)
#define CAN13_CLK_RREQ_HIGHCLK_PPM_OFFSET    (0x1e8U)
#define CAN14_CLK_RREQ_REF_CLKCNT_OFFSET     (0x1ecU)
#define CAN14_CLK_RREQ_HIGHCLKCNT_OFFSET     (0x1f0U)
#define CAN14_CLK_RREQ_THRESHOLD_OFFSET      (0x1f4U)
#define CAN14_CLK_RREQ_HIGHCLK_PPM_OFFSET    (0x1f8U)
#define CAN15_CLK_RREQ_REF_CLKCNT_OFFSET     (0x1fcU)
#define CAN15_CLK_RREQ_HIGHCLKCNT_OFFSET     (0x200U)
#define CAN15_CLK_RREQ_THRESHOLD_OFFSET      (0x204U)
#define CAN15_CLK_RREQ_HIGHCLK_PPM_OFFSET    (0x208U)
#define FLEXCAN_PARITY_IRQ_OFFSET            (0x20cU)
#define LIN_PARITY_STATUS0_OFFSET            (0x210U)
#define LIN_PARITY_STATUS1_OFFSET            (0x214U)
#define LIN_IPG_STOP_OFFSET                  (0x218U)
#define RSV0_OFFSET                          (0x21cU)
#define RSV1_OFFSET                          (0x220U)

#define LOCAL_RST_CFG_LSP_TIMER_PCLK_LOCAL_SW_RST_N_CFG_U32                           (0x00400000UL) /*None*/
#define LOCAL_RST_CFG_LSP_TIMER_PCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                     (22U)
#define LOCAL_RST_CFG_LSP_WDT0_WCLK_LOCAL_SW_RST_N_CFG_U32                            (0x00200000UL) /*None*/
#define LOCAL_RST_CFG_LSP_WDT0_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                      (21U)
#define LOCAL_RST_CFG_LSP_WDT1_WCLK_LOCAL_SW_RST_N_CFG_U32                            (0x00100000UL) /*None*/
#define LOCAL_RST_CFG_LSP_WDT1_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                      (20U)
#define LOCAL_RST_CFG_LSP_WDT2_WCLK_LOCAL_SW_RST_N_CFG_U32                            (0x00080000UL) /*None*/
#define LOCAL_RST_CFG_LSP_WDT2_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                      (19U)
#define LOCAL_RST_CFG_LSP_WDT3_WCLK_LOCAL_SW_RST_N_CFG_U32                            (0x00040000UL) /*None*/
#define LOCAL_RST_CFG_LSP_WDT3_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                      (18U)
#define LOCAL_RST_CFG_LSP_WDT4_WCLK_LOCAL_SW_RST_N_CFG_U32                            (0x00020000UL) /*None*/
#define LOCAL_RST_CFG_LSP_WDT4_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                      (17U)
#define LOCAL_RST_CFG_LSP_WDT5_WCLK_LOCAL_SW_RST_N_CFG_U32                            (0x00010000UL) /*None*/
#define LOCAL_RST_CFG_LSP_WDT5_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                      (16U)
#define LOCAL_RST_CFG_LSP_RAY0_WCLK_LOCAL_SW_RST_N_CFG_U32                            (0x00008000UL) /*None*/
#define LOCAL_RST_CFG_LSP_RAY0_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                      (15U)
#define LOCAL_RST_CFG_LSP_RAY1_WCLK_LOCAL_SW_RST_N_CFG_U32                            (0x00004000UL) /*None*/
#define LOCAL_RST_CFG_LSP_RAY1_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                      (14U)
#define LOCAL_RST_CFG_LSP_TIMER0_WCLK_LOCAL_SW_RST_N_CFG_U32                          (0x00002000UL) /*None*/
#define LOCAL_RST_CFG_LSP_TIMER0_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                    (13U)
#define LOCAL_RST_CFG_LSP_TIMER1_WCLK_LOCAL_SW_RST_N_CFG_U32                          (0x00001000UL) /*None*/
#define LOCAL_RST_CFG_LSP_TIMER1_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                    (12U)
#define LOCAL_RST_CFG_LSP_TIMER2_WCLK_LOCAL_SW_RST_N_CFG_U32                          (0x00000800UL) /*None*/
#define LOCAL_RST_CFG_LSP_TIMER2_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                    (11U)
#define LOCAL_RST_CFG_LSP_TIMER3_WCLK_LOCAL_SW_RST_N_CFG_U32                          (0x00000400UL) /*None*/
#define LOCAL_RST_CFG_LSP_TIMER3_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                    (10U)
#define LOCAL_RST_CFG_LSP_TIMER4_WCLK_LOCAL_SW_RST_N_CFG_U32                          (0x00000200UL) /*None*/
#define LOCAL_RST_CFG_LSP_TIMER4_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                    (9U)
#define LOCAL_RST_CFG_LSP_TIMER5_WCLK_LOCAL_SW_RST_N_CFG_U32                          (0x00000100UL) /*None*/
#define LOCAL_RST_CFG_LSP_TIMER5_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                    (8U)
#define LOCAL_RST_CFG_LSP_TIMER6_WCLK_LOCAL_SW_RST_N_CFG_U32                          (0x00000080UL) /*None*/
#define LOCAL_RST_CFG_LSP_TIMER6_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                    (7U)
#define LOCAL_RST_CFG_LSP_TIMER7_WCLK_LOCAL_SW_RST_N_CFG_U32                          (0x00000040UL) /*None*/
#define LOCAL_RST_CFG_LSP_TIMER7_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                    (6U)
#define LOCAL_RST_CFG_LSP_LIN0_WCLK_LOCAL_SW_RST_N_CFG_U32                            (0x00000020UL) /*None*/
#define LOCAL_RST_CFG_LSP_LIN0_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                      (5U)
#define LOCAL_RST_CFG_LSP_LIN1_WCLK_LOCAL_SW_RST_N_CFG_U32                            (0x00000010UL) /*None*/
#define LOCAL_RST_CFG_LSP_LIN1_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                      (4U)
#define LOCAL_RST_CFG_LSP_LIN2_WCLK_LOCAL_SW_RST_N_CFG_U32                            (0x00000008UL) /*None*/
#define LOCAL_RST_CFG_LSP_LIN2_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                      (3U)
#define LOCAL_RST_CFG_LSP_LIN3_WCLK_LOCAL_SW_RST_N_CFG_U32                            (0x00000004UL) /*None*/
#define LOCAL_RST_CFG_LSP_LIN3_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                      (2U)
#define LOCAL_RST_CFG_LSP_LIN4_WCLK_LOCAL_SW_RST_N_CFG_U32                            (0x00000002UL) /*None*/
#define LOCAL_RST_CFG_LSP_LIN4_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                      (1U)
#define LOCAL_RST_CFG_LSP_LIN5_WCLK_LOCAL_SW_RST_N_CFG_U32                            (0x00000001UL) /*None*/
#define LOCAL_RST_CFG_LSP_LIN5_WCLK_LOCAL_SW_RST_N_CFG_SHIFT_U32                      (0U)

#define CLK_GATE_CFG_LSP_WDT0_CLK_GATE_EN_CFG_U32                                     (0x00200000UL) /*None*/
#define CLK_GATE_CFG_LSP_WDT0_CLK_GATE_EN_CFG_SHIFT_U32                               (21U)
#define CLK_GATE_CFG_LSP_WDT1_CLK_GATE_EN_CFG_U32                                     (0x00100000UL) /*None*/
#define CLK_GATE_CFG_LSP_WDT1_CLK_GATE_EN_CFG_SHIFT_U32                               (20U)
#define CLK_GATE_CFG_LSP_WDT2_CLK_GATE_EN_CFG_U32                                     (0x00080000UL) /*None*/
#define CLK_GATE_CFG_LSP_WDT2_CLK_GATE_EN_CFG_SHIFT_U32                               (19U)
#define CLK_GATE_CFG_LSP_WDT3_CLK_GATE_EN_CFG_U32                                     (0x00040000UL) /*None*/
#define CLK_GATE_CFG_LSP_WDT3_CLK_GATE_EN_CFG_SHIFT_U32                               (18U)
#define CLK_GATE_CFG_LSP_WDT4_CLK_GATE_EN_CFG_U32                                     (0x00020000UL) /*None*/
#define CLK_GATE_CFG_LSP_WDT4_CLK_GATE_EN_CFG_SHIFT_U32                               (17U)
#define CLK_GATE_CFG_LSP_WDT5_CLK_GATE_EN_CFG_U32                                     (0x00010000UL) /*None*/
#define CLK_GATE_CFG_LSP_WDT5_CLK_GATE_EN_CFG_SHIFT_U32                               (16U)
#define CLK_GATE_CFG_LSP_RAY0_CLK_GATE_EN_CFG_U32                                     (0x00008000UL) /*None*/
#define CLK_GATE_CFG_LSP_RAY0_CLK_GATE_EN_CFG_SHIFT_U32                               (15U)
#define CLK_GATE_CFG_LSP_RAY1_CLK_GATE_EN_CFG_U32                                     (0x00004000UL) /*None*/
#define CLK_GATE_CFG_LSP_RAY1_CLK_GATE_EN_CFG_SHIFT_U32                               (14U)
#define CLK_GATE_CFG_LSP_TIMER0_WCLK_GATE_EN_CFG_U32                                  (0x00002000UL) /*None*/
#define CLK_GATE_CFG_LSP_TIMER0_WCLK_GATE_EN_CFG_SHIFT_U32                            (13U)
#define CLK_GATE_CFG_LSP_TIMER1_WCLK_GATE_EN_CFG_U32                                  (0x00001000UL) /*None*/
#define CLK_GATE_CFG_LSP_TIMER1_WCLK_GATE_EN_CFG_SHIFT_U32                            (12U)
#define CLK_GATE_CFG_LSP_TIMER2_WCLK_GATE_EN_CFG_U32                                  (0x00000800UL) /*None*/
#define CLK_GATE_CFG_LSP_TIMER2_WCLK_GATE_EN_CFG_SHIFT_U32                            (11U)
#define CLK_GATE_CFG_LSP_TIMER3_WCLK_GATE_EN_CFG_U32                                  (0x00000400UL) /*None*/
#define CLK_GATE_CFG_LSP_TIMER3_WCLK_GATE_EN_CFG_SHIFT_U32                            (10U)
#define CLK_GATE_CFG_LSP_TIMER4_WCLK_GATE_EN_CFG_U32                                  (0x00000200UL) /*None*/
#define CLK_GATE_CFG_LSP_TIMER4_WCLK_GATE_EN_CFG_SHIFT_U32                            (9U)
#define CLK_GATE_CFG_LSP_TIMER5_WCLK_GATE_EN_CFG_U32                                  (0x00000100UL) /*None*/
#define CLK_GATE_CFG_LSP_TIMER5_WCLK_GATE_EN_CFG_SHIFT_U32                            (8U)
#define CLK_GATE_CFG_LSP_TIMER6_WCLK_GATE_EN_CFG_U32                                  (0x00000080UL) /*None*/
#define CLK_GATE_CFG_LSP_TIMER6_WCLK_GATE_EN_CFG_SHIFT_U32                            (7U)
#define CLK_GATE_CFG_LSP_TIMER7_WCLK_GATE_EN_CFG_U32                                  (0x00000040UL) /*None*/
#define CLK_GATE_CFG_LSP_TIMER7_WCLK_GATE_EN_CFG_SHIFT_U32                            (6U)
#define CLK_GATE_CFG_LSP_LIN0_CLK_GATE_EN_CFG_U32                                     (0x00000020UL) /*None*/
#define CLK_GATE_CFG_LSP_LIN0_CLK_GATE_EN_CFG_SHIFT_U32                               (5U)
#define CLK_GATE_CFG_LSP_LIN1_CLK_GATE_EN_CFG_U32                                     (0x00000010UL) /*None*/
#define CLK_GATE_CFG_LSP_LIN1_CLK_GATE_EN_CFG_SHIFT_U32                               (4U)
#define CLK_GATE_CFG_LSP_LIN2_CLK_GATE_EN_CFG_U32                                     (0x00000008UL) /*None*/
#define CLK_GATE_CFG_LSP_LIN2_CLK_GATE_EN_CFG_SHIFT_U32                               (3U)
#define CLK_GATE_CFG_LSP_LIN3_CLK_GATE_EN_CFG_U32                                     (0x00000004UL) /*None*/
#define CLK_GATE_CFG_LSP_LIN3_CLK_GATE_EN_CFG_SHIFT_U32                               (2U)
#define CLK_GATE_CFG_LSP_LIN4_CLK_GATE_EN_CFG_U32                                     (0x00000002UL) /*None*/
#define CLK_GATE_CFG_LSP_LIN4_CLK_GATE_EN_CFG_SHIFT_U32                               (1U)
#define CLK_GATE_CFG_LSP_LIN5_CLK_GATE_EN_CFG_U32                                     (0x00000001UL) /*None*/
#define CLK_GATE_CFG_LSP_LIN5_CLK_GATE_EN_CFG_SHIFT_U32                               (0U)

#define PARITY_CFG_RAY0_RDATA_PARITY_ERR_INJECT_U32                                   (0x40000000UL) /*None*/
#define PARITY_CFG_RAY0_RDATA_PARITY_ERR_INJECT_SHIFT_U32                             (30U)
#define PARITY_CFG_RAY0_ADDR_PARITY_IRQ_U32                                           (0x20000000UL) /*None*/
#define PARITY_CFG_RAY0_ADDR_PARITY_IRQ_SHIFT_U32                                     (29U)
#define PARITY_CFG_RAY0_WDATA_PARITY_IRQ_U32                                          (0x10000000UL) /*None*/
#define PARITY_CFG_RAY0_WDATA_PARITY_IRQ_SHIFT_U32                                    (28U)
#define PARITY_CFG_RAY0_ADDR_PARITY_IRQ_CLR_U32                                       (0x08000000UL) /*None*/
#define PARITY_CFG_RAY0_ADDR_PARITY_IRQ_CLR_SHIFT_U32                                 (27U)
#define PARITY_CFG_RAY0_WDATA_PARITY_IRQ_CLR_U32                                      (0x04000000UL) /*None*/
#define PARITY_CFG_RAY0_WDATA_PARITY_IRQ_CLR_SHIFT_U32                                (26U)
#define PARITY_CFG_RAY0_ADDR_PARITY_IRQ_MASK_U32                                      (0x02000000UL) /*None*/
#define PARITY_CFG_RAY0_ADDR_PARITY_IRQ_MASK_SHIFT_U32                                (25U)
#define PARITY_CFG_RAY0_WDATA_PARITY_IRQ_MASK_U32                                     (0x01000000UL) /*None*/
#define PARITY_CFG_RAY0_WDATA_PARITY_IRQ_MASK_SHIFT_U32                               (24U)
#define PARITY_CFG_RAY1_ADDR_PARITY_IRQ_U32                                           (0x00800000UL) /*None*/
#define PARITY_CFG_RAY1_ADDR_PARITY_IRQ_SHIFT_U32                                     (23U)
#define PARITY_CFG_RAY1_WDATA_PARITY_IRQ_U32                                          (0x00400000UL) /*None*/
#define PARITY_CFG_RAY1_WDATA_PARITY_IRQ_SHIFT_U32                                    (22U)
#define PARITY_CFG_RAY1_RDATA_PARITY_ERR_INJECT_U32                                   (0x00200000UL) /*None*/
#define PARITY_CFG_RAY1_RDATA_PARITY_ERR_INJECT_SHIFT_U32                             (21U)
#define PARITY_CFG_RAY1_ADDR_PARITY_IRQ_CLR_U32                                       (0x00100000UL) /*None*/
#define PARITY_CFG_RAY1_ADDR_PARITY_IRQ_CLR_SHIFT_U32                                 (20U)
#define PARITY_CFG_RAY1_WDATA_PARITY_IRQ_CLR_U32                                      (0x00080000UL) /*None*/
#define PARITY_CFG_RAY1_WDATA_PARITY_IRQ_CLR_SHIFT_U32                                (19U)
#define PARITY_CFG_RAY1_ADDR_PARITY_IRQ_MASK_U32                                      (0x00040000UL) /*None*/
#define PARITY_CFG_RAY1_ADDR_PARITY_IRQ_MASK_SHIFT_U32                                (18U)
#define PARITY_CFG_RAY1_WDATA_PARITY_IRQ_MASK_U32                                     (0x00020000UL) /*None*/
#define PARITY_CFG_RAY1_WDATA_PARITY_IRQ_MASK_SHIFT_U32                               (17U)
#define PARITY_CFG_RAY0_HRDATA_PARITY_IRQ_U32                                         (0x00010000UL) /*None*/
#define PARITY_CFG_RAY0_HRDATA_PARITY_IRQ_SHIFT_U32                                   (16U)
#define PARITY_CFG_RAY0_HADDR_PARITY_ERR_INJECT_U32                                   (0x00008000UL) /*None*/
#define PARITY_CFG_RAY0_HADDR_PARITY_ERR_INJECT_SHIFT_U32                             (15U)
#define PARITY_CFG_RAY0_HWDATA_PARITY_ERR_INJECT_U32                                  (0x00004000UL) /*None*/
#define PARITY_CFG_RAY0_HWDATA_PARITY_ERR_INJECT_SHIFT_U32                            (14U)
#define PARITY_CFG_RAY0_HRDATA_PARITY_IRQ_CLR_U32                                     (0x00002000UL) /*None*/
#define PARITY_CFG_RAY0_HRDATA_PARITY_IRQ_CLR_SHIFT_U32                               (13U)
#define PARITY_CFG_RAY0_HRDATA_PARITY_IRQ_MASK_U32                                    (0x00001000UL) /*None*/
#define PARITY_CFG_RAY0_HRDATA_PARITY_IRQ_MASK_SHIFT_U32                              (12U)
#define PARITY_CFG_RAY1_HRDATA_PARITY_IRQ_U32                                         (0x00000800UL) /*None*/
#define PARITY_CFG_RAY1_HRDATA_PARITY_IRQ_SHIFT_U32                                   (11U)
#define PARITY_CFG_RAY1_HADDR_PARITY_ERR_INJECT_U32                                   (0x00000400UL) /*None*/
#define PARITY_CFG_RAY1_HADDR_PARITY_ERR_INJECT_SHIFT_U32                             (10U)
#define PARITY_CFG_RAY1_HWDATA_PARITY_ERR_INJECT_U32                                  (0x00000200UL) /*None*/
#define PARITY_CFG_RAY1_HWDATA_PARITY_ERR_INJECT_SHIFT_U32                            (9U)
#define PARITY_CFG_RAY1_HRDATA_PARITY_IRQ_CLR_U32                                     (0x00000100UL) /*None*/
#define PARITY_CFG_RAY1_HRDATA_PARITY_IRQ_CLR_SHIFT_U32                               (8U)
#define PARITY_CFG_RAY1_HRDATA_PARITY_IRQ_MASK_U32                                    (0x00000080UL) /*None*/
#define PARITY_CFG_RAY1_HRDATA_PARITY_IRQ_MASK_SHIFT_U32                              (7U)
#define PARITY_CFG_LSP_ADDR_PARITY_IRQ_U32                                            (0x00000040UL) /*None*/
#define PARITY_CFG_LSP_ADDR_PARITY_IRQ_SHIFT_U32                                      (6U)
#define PARITY_CFG_LSP_WDATA_PARITY_IRQ_U32                                           (0x00000020UL) /*None*/
#define PARITY_CFG_LSP_WDATA_PARITY_IRQ_SHIFT_U32                                     (5U)
#define PARITY_CFG_LSP_RDATA_PARITY_ERR_INJECT_U32                                    (0x00000010UL) /*None*/
#define PARITY_CFG_LSP_RDATA_PARITY_ERR_INJECT_SHIFT_U32                              (4U)
#define PARITY_CFG_LSP_ADDR_PARITY_IRQ_CLR_U32                                        (0x00000008UL) /*None*/
#define PARITY_CFG_LSP_ADDR_PARITY_IRQ_CLR_SHIFT_U32                                  (3U)
#define PARITY_CFG_LSP_WDATA_PARITY_IRQ_CLR_U32                                       (0x00000004UL) /*None*/
#define PARITY_CFG_LSP_WDATA_PARITY_IRQ_CLR_SHIFT_U32                                 (2U)
#define PARITY_CFG_LSP_ADDR_PARITY_IRQ_MASK_U32                                       (0x00000002UL) /*None*/
#define PARITY_CFG_LSP_ADDR_PARITY_IRQ_MASK_SHIFT_U32                                 (1U)
#define PARITY_CFG_LSP_WDATA_PARITY_IRQ_MASK_U32                                      (0x00000001UL) /*None*/
#define PARITY_CFG_LSP_WDATA_PARITY_IRQ_MASK_SHIFT_U32                                (0U)

#define LSP_SFT_CFG_CTRL_WDT_SEL_U32                                                  (0x00800000UL) /*1:DW_wdt 0:wwdg*/
#define LSP_SFT_CFG_CTRL_WDT_SEL_SHIFT_U32                                            (23U)
#define LSP_SFT_CFG_CTRL_FLEXRAY0_STB_U32                                             (0x00780000UL) /*None*/
#define LSP_SFT_CFG_CTRL_FLEXRAY0_STB_SHIFT_U32                                       (19U)
#define LSP_SFT_CFG_CTRL_FLEXRAY1_STB_U32                                             (0x00078000UL) /*None*/
#define LSP_SFT_CFG_CTRL_FLEXRAY1_STB_SHIFT_U32                                       (15U)
#define LSP_SFT_CFG_CTRL_LIN_WCLK_SEL_U32                                             (0x00004000UL) /*1:10MHz  0:lsp_wclk_sel=0 200MHz,lsp_wclk_sel=1 100MHz*/
#define LSP_SFT_CFG_CTRL_LIN_WCLK_SEL_SHIFT_U32                                       (14U)
#define LSP_SFT_CFG_CTRL_LSP_WCLK_SEL_U32                                             (0x00002000UL) /*1:100MHz 0:200MHz*/
#define LSP_SFT_CFG_CTRL_LSP_WCLK_SEL_SHIFT_U32                                       (13U)
#define LSP_SFT_CFG_CTRL_WDT_SFT_CFG_CTRL_U32                                         (0x00000FFFUL) /*wdt_sft_cfg_ctrl[0]:wdt0_pause wdt_sft_cfg_ctrl[1]:wdt0_speed_up wdt_sft_cfg_ctrl[2]:wdt1_pause wdt_sft_cfg_ctrl[3]:wdt1_speed_up wdt_sft_cfg_ctrl[4]:wdt2_pause wdt_sft_cfg_ctrl[5]:wdt2_speed_up wdt_sft_cfg_ctrl[6]:wdt3_pause wdt_sft_cfg_ctrl[7]:wdt3_speed_up wdt_sft_cfg_ctrl[8]:wdt4_pause wdt_sft_cfg_ctrl[9]:wdt4_speed_up wdt_sft_cfg_ctrl[10]:wdt5_pause wdt_sft_cfg_ctrl[11]:wdt5_speed_up*/
#define LSP_SFT_CFG_CTRL_WDT_SFT_CFG_CTRL_SHIFT_U32                                   (8U)

#define TIMER_SFT_CFG_CTRL_TIMER_SFT_CFG_CTRL_U32                                     (0x000000FFUL) /*timer_sft_cfg_ctrl[0]:timer_1_pause timer_sft_cfg_ctrl[1]:timer_2_pause timer_sft_cfg_ctrl[2]:timer_3_pause timer_sft_cfg_ctrl[3]:timer_4_pause timer_sft_cfg_ctrl[4]:timer_5_pause timer_sft_cfg_ctrl[5]:timer_6_pause timer_sft_cfg_ctrl[6]:timer_7_pause timer_sft_cfg_ctrl[7]:timer_8_pause*/
#define TIMER_SFT_CFG_CTRL_TIMER_SFT_CFG_CTRL_SHIFT_U32                               (0U)

#define CAN_SFT_CFG_CTRL_LSP_CAN_VR_MUX_U32                                           (0x00000001UL) /*None*/
#define CAN_SFT_CFG_CTRL_LSP_CAN_VR_MUX_SHIFT_U32                                     (0U)

#define CAN0_IP_CFG_LSP_CAN0_IP_CFG_U32                                               (0x07FFFFFEUL) /*None*/
#define CAN0_IP_CFG_LSP_CAN0_IP_CFG_SHIFT_U32                                         (1U)
#define CAN0_IP_CFG_LSP_CAN0_IP_IPG_STOP_ACK_U32                                      (0x00000001UL) /*None*/
#define CAN0_IP_CFG_LSP_CAN0_IP_IPG_STOP_ACK_SHIFT_U32                                (0U)

#define CAN1_IP_CFG_LSP_CAN1_IP_CFG_U32                                               (0x07FFFFFEUL) /*None*/
#define CAN1_IP_CFG_LSP_CAN1_IP_CFG_SHIFT_U32                                         (1U)
#define CAN1_IP_CFG_LSP_CAN1_IP_IPG_STOP_ACK_U32                                      (0x00000001UL) /*None*/
#define CAN1_IP_CFG_LSP_CAN1_IP_IPG_STOP_ACK_SHIFT_U32                                (0U)

#define CAN2_IP_CFG_LSP_CAN2_IP_CFG_U32                                               (0x07FFFFFEUL) /*None*/
#define CAN2_IP_CFG_LSP_CAN2_IP_CFG_SHIFT_U32                                         (1U)
#define CAN2_IP_CFG_LSP_CAN2_IP_IPG_STOP_ACK_U32                                      (0x00000001UL) /*None*/
#define CAN2_IP_CFG_LSP_CAN2_IP_IPG_STOP_ACK_SHIFT_U32                                (0U)

#define CAN3_IP_CFG_LSP_CAN3_IP_CFG_U32                                               (0x07FFFFFEUL) /*None*/
#define CAN3_IP_CFG_LSP_CAN3_IP_CFG_SHIFT_U32                                         (1U)
#define CAN3_IP_CFG_LSP_CAN3_IP_IPG_STOP_ACK_U32                                      (0x00000001UL) /*None*/
#define CAN3_IP_CFG_LSP_CAN3_IP_IPG_STOP_ACK_SHIFT_U32                                (0U)

#define CAN4_IP_CFG_LSP_CAN4_IP_CFG_U32                                               (0x07FFFFFEUL) /*None*/
#define CAN4_IP_CFG_LSP_CAN4_IP_CFG_SHIFT_U32                                         (1U)
#define CAN4_IP_CFG_LSP_CAN4_IP_IPG_STOP_ACK_U32                                      (0x00000001UL) /*None*/
#define CAN4_IP_CFG_LSP_CAN4_IP_IPG_STOP_ACK_SHIFT_U32                                (0U)

#define CAN5_IP_CFG_LSP_CAN5_IP_CFG_U32                                               (0x07FFFFFEUL) /*None*/
#define CAN5_IP_CFG_LSP_CAN5_IP_CFG_SHIFT_U32                                         (1U)
#define CAN5_IP_CFG_LSP_CAN5_IP_IPG_STOP_ACK_U32                                      (0x00000001UL) /*None*/
#define CAN5_IP_CFG_LSP_CAN5_IP_IPG_STOP_ACK_SHIFT_U32                                (0U)

#define CAN6_IP_CFG_LSP_CAN6_IP_CFG_U32                                               (0x07FFFFFEUL) /*None*/
#define CAN6_IP_CFG_LSP_CAN6_IP_CFG_SHIFT_U32                                         (1U)
#define CAN6_IP_CFG_LSP_CAN6_IP_IPG_STOP_ACK_U32                                      (0x00000001UL) /*None*/
#define CAN6_IP_CFG_LSP_CAN6_IP_IPG_STOP_ACK_SHIFT_U32                                (0U)

#define CAN7_IP_CFG_LSP_CAN7_IP_CFG_U32                                               (0x07FFFFFEUL) /*None*/
#define CAN7_IP_CFG_LSP_CAN7_IP_CFG_SHIFT_U32                                         (1U)
#define CAN7_IP_CFG_LSP_CAN7_IP_IPG_STOP_ACK_U32                                      (0x00000001UL) /*None*/
#define CAN7_IP_CFG_LSP_CAN7_IP_IPG_STOP_ACK_SHIFT_U32                                (0U)

#define CAN8_IP_CFG_LSP_CAN8_IP_CFG_U32                                               (0x07FFFFFEUL) /*None*/
#define CAN8_IP_CFG_LSP_CAN8_IP_CFG_SHIFT_U32                                         (1U)
#define CAN8_IP_CFG_LSP_CAN8_IP_IPG_STOP_ACK_U32                                      (0x00000001UL) /*None*/
#define CAN8_IP_CFG_LSP_CAN8_IP_IPG_STOP_ACK_SHIFT_U32                                (0U)

#define CAN9_IP_CFG_LSP_CAN9_IP_CFG_U32                                               (0x07FFFFFEUL) /*None*/
#define CAN9_IP_CFG_LSP_CAN9_IP_CFG_SHIFT_U32                                         (1U)
#define CAN9_IP_CFG_LSP_CAN9_IP_IPG_STOP_ACK_U32                                      (0x00000001UL) /*None*/
#define CAN9_IP_CFG_LSP_CAN9_IP_IPG_STOP_ACK_SHIFT_U32                                (0U)

#define CAN10_IP_CFG_LSP_CAN10_IP_CFG_U32                                             (0x07FFFFFEUL) /*None*/
#define CAN10_IP_CFG_LSP_CAN10_IP_CFG_SHIFT_U32                                       (1U)
#define CAN10_IP_CFG_LSP_CAN10_IP_IPG_STOP_ACK_U32                                    (0x00000001UL) /*None*/
#define CAN10_IP_CFG_LSP_CAN10_IP_IPG_STOP_ACK_SHIFT_U32                              (0U)

#define CAN11_IP_CFG_LSP_CAN11_IP_CFG_U32                                             (0x07FFFFFEUL) /*None*/
#define CAN11_IP_CFG_LSP_CAN11_IP_CFG_SHIFT_U32                                       (1U)
#define CAN11_IP_CFG_LSP_CAN11_IP_IPG_STOP_ACK_U32                                    (0x00000001UL) /*None*/
#define CAN11_IP_CFG_LSP_CAN11_IP_IPG_STOP_ACK_SHIFT_U32                              (0U)

#define CAN12_IP_CFG_LSP_CAN12_IP_CFG_U32                                             (0x07FFFFFEUL) /*None*/
#define CAN12_IP_CFG_LSP_CAN12_IP_CFG_SHIFT_U32                                       (1U)
#define CAN12_IP_CFG_LSP_CAN12_IP_IPG_STOP_ACK_U32                                    (0x00000001UL) /*None*/
#define CAN12_IP_CFG_LSP_CAN12_IP_IPG_STOP_ACK_SHIFT_U32                              (0U)

#define CAN13_IP_CFG_LSP_CAN13_IP_CFG_U32                                             (0x07FFFFFEUL) /*None*/
#define CAN13_IP_CFG_LSP_CAN13_IP_CFG_SHIFT_U32                                       (1U)
#define CAN13_IP_CFG_LSP_CAN13_IP_IPG_STOP_ACK_U32                                    (0x00000001UL) /*None*/
#define CAN13_IP_CFG_LSP_CAN13_IP_IPG_STOP_ACK_SHIFT_U32                              (0U)

#define CAN14_IP_CFG_LSP_CAN14_IP_CFG_U32                                             (0x07FFFFFEUL) /*None*/
#define CAN14_IP_CFG_LSP_CAN14_IP_CFG_SHIFT_U32                                       (1U)
#define CAN14_IP_CFG_LSP_CAN14_IP_IPG_STOP_ACK_U32                                    (0x00000001UL) /*None*/
#define CAN14_IP_CFG_LSP_CAN14_IP_IPG_STOP_ACK_SHIFT_U32                              (0U)

#define CAN15_IP_CFG_LSP_CAN15_IP_CFG_U32                                             (0x07FFFFFEUL) /*None*/
#define CAN15_IP_CFG_LSP_CAN15_IP_CFG_SHIFT_U32                                       (1U)
#define CAN15_IP_CFG_LSP_CAN15_IP_IPG_STOP_ACK_U32                                    (0x00000001UL) /*None*/
#define CAN15_IP_CFG_LSP_CAN15_IP_IPG_STOP_ACK_SHIFT_U32                              (0U)

#define CAN0_SR_CFG_CANFD0_WCLK_DIV_COFF_U32                                          (0x0000003CUL) /*None*/
#define CAN0_SR_CFG_CANFD0_WCLK_DIV_COFF_SHIFT_U32                                    (2U)
#define CAN0_SR_CFG_LSP_CAN0_SR_CFG_U32                                               (0x00000003UL) /*None*/
#define CAN0_SR_CFG_LSP_CAN0_SR_CFG_SHIFT_U32                                         (0U)

#define CAN1_SR_CFG_CANFD1_WCLK_DIV_COFF_U32                                          (0x0000003CUL) /*None*/
#define CAN1_SR_CFG_CANFD1_WCLK_DIV_COFF_SHIFT_U32                                    (2U)
#define CAN1_SR_CFG_LSP_CAN1_SR_CFG_U32                                               (0x00000003UL) /*None*/
#define CAN1_SR_CFG_LSP_CAN1_SR_CFG_SHIFT_U32                                         (0U)

#define CAN2_SR_CFG_CANFD2_WCLK_DIV_COFF_U32                                          (0x0000003CUL) /*None*/
#define CAN2_SR_CFG_CANFD2_WCLK_DIV_COFF_SHIFT_U32                                    (2U)
#define CAN2_SR_CFG_LSP_CAN2_SR_CFG_U32                                               (0x00000003UL) /*None*/
#define CAN2_SR_CFG_LSP_CAN2_SR_CFG_SHIFT_U32                                         (0U)

#define CAN3_SR_CFG_CANFD3_WCLK_DIV_COFF_U32                                          (0x0000003CUL) /*None*/
#define CAN3_SR_CFG_CANFD3_WCLK_DIV_COFF_SHIFT_U32                                    (2U)
#define CAN3_SR_CFG_LSP_CAN3_SR_CFG_U32                                               (0x00000003UL) /*None*/
#define CAN3_SR_CFG_LSP_CAN3_SR_CFG_SHIFT_U32                                         (0U)

#define CAN4_SR_CFG_CANFD4_WCLK_DIV_COFF_U32                                          (0x0000003CUL) /*None*/
#define CAN4_SR_CFG_CANFD4_WCLK_DIV_COFF_SHIFT_U32                                    (2U)
#define CAN4_SR_CFG_LSP_CAN4_SR_CFG_U32                                               (0x00000003UL) /*None*/
#define CAN4_SR_CFG_LSP_CAN4_SR_CFG_SHIFT_U32                                         (0U)

#define CAN5_SR_CFG_CANFD5_WCLK_DIV_COFF_U32                                          (0x0000003CUL) /*None*/
#define CAN5_SR_CFG_CANFD5_WCLK_DIV_COFF_SHIFT_U32                                    (2U)
#define CAN5_SR_CFG_LSP_CAN5_SR_CFG_U32                                               (0x00000003UL) /*None*/
#define CAN5_SR_CFG_LSP_CAN5_SR_CFG_SHIFT_U32                                         (0U)

#define CAN6_SR_CFG_CANFD6_WCLK_DIV_COFF_U32                                          (0x0000003CUL) /*None*/
#define CAN6_SR_CFG_CANFD6_WCLK_DIV_COFF_SHIFT_U32                                    (2U)
#define CAN6_SR_CFG_LSP_CAN6_SR_CFG_U32                                               (0x00000003UL) /*None*/
#define CAN6_SR_CFG_LSP_CAN6_SR_CFG_SHIFT_U32                                         (0U)

#define CAN7_SR_CFG_CANFD7_WCLK_DIV_COFF_U32                                          (0x0000003CUL) /*None*/
#define CAN7_SR_CFG_CANFD7_WCLK_DIV_COFF_SHIFT_U32                                    (2U)
#define CAN7_SR_CFG_LSP_CAN7_SR_CFG_U32                                               (0x00000003UL) /*None*/
#define CAN7_SR_CFG_LSP_CAN7_SR_CFG_SHIFT_U32                                         (0U)

#define CAN8_SR_CFG_CANFD8_WCLK_DIV_COFF_U32                                          (0x0000003CUL) /*None*/
#define CAN8_SR_CFG_CANFD8_WCLK_DIV_COFF_SHIFT_U32                                    (2U)
#define CAN8_SR_CFG_LSP_CAN8_SR_CFG_U32                                               (0x00000003UL) /*None*/
#define CAN8_SR_CFG_LSP_CAN8_SR_CFG_SHIFT_U32                                         (0U)

#define CAN9_SR_CFG_CANFD9_WCLK_DIV_COFF_U32                                          (0x0000003CUL) /*None*/
#define CAN9_SR_CFG_CANFD9_WCLK_DIV_COFF_SHIFT_U32                                    (2U)
#define CAN9_SR_CFG_LSP_CAN9_SR_CFG_U32                                               (0x00000003UL) /*None*/
#define CAN9_SR_CFG_LSP_CAN9_SR_CFG_SHIFT_U32                                         (0U)

#define CAN10_SR_CFG_CANFD10_WCLK_DIV_COFF_U32                                        (0x0000003CUL) /*None*/
#define CAN10_SR_CFG_CANFD10_WCLK_DIV_COFF_SHIFT_U32                                  (2U)
#define CAN10_SR_CFG_LSP_CAN10_SR_CFG_U32                                             (0x00000003UL) /*None*/
#define CAN10_SR_CFG_LSP_CAN10_SR_CFG_SHIFT_U32                                       (0U)

#define CAN11_SR_CFG_CANFD11_WCLK_DIV_COFF_U32                                        (0x0000003CUL) /*None*/
#define CAN11_SR_CFG_CANFD11_WCLK_DIV_COFF_SHIFT_U32                                  (2U)
#define CAN11_SR_CFG_LSP_CAN11_SR_CFG_U32                                             (0x00000003UL) /*None*/
#define CAN11_SR_CFG_LSP_CAN11_SR_CFG_SHIFT_U32                                       (0U)

#define CAN12_SR_CFG_CANFD12_WCLK_DIV_COFF_U32                                        (0x0000003CUL) /*None*/
#define CAN12_SR_CFG_CANFD12_WCLK_DIV_COFF_SHIFT_U32                                  (2U)
#define CAN12_SR_CFG_LSP_CAN12_SR_CFG_U32                                             (0x00000003UL) /*None*/
#define CAN12_SR_CFG_LSP_CAN12_SR_CFG_SHIFT_U32                                       (0U)

#define CAN13_SR_CFG_CANFD13_WCLK_DIV_COFF_U32                                        (0x0000003CUL) /*None*/
#define CAN13_SR_CFG_CANFD13_WCLK_DIV_COFF_SHIFT_U32                                  (2U)
#define CAN13_SR_CFG_LSP_CAN13_SR_CFG_U32                                             (0x00000003UL) /*None*/
#define CAN13_SR_CFG_LSP_CAN13_SR_CFG_SHIFT_U32                                       (0U)

#define CAN14_SR_CFG_CANFD14_WCLK_DIV_COFF_U32                                        (0x0000003CUL) /*None*/
#define CAN14_SR_CFG_CANFD14_WCLK_DIV_COFF_SHIFT_U32                                  (2U)
#define CAN14_SR_CFG_LSP_CAN14_SR_CFG_U32                                             (0x00000003UL) /*None*/
#define CAN14_SR_CFG_LSP_CAN14_SR_CFG_SHIFT_U32                                       (0U)

#define CAN15_SR_CFG_CANFD15_WCLK_DIV_COFF_U32                                        (0x0000003CUL) /*None*/
#define CAN15_SR_CFG_CANFD15_WCLK_DIV_COFF_SHIFT_U32                                  (2U)
#define CAN15_SR_CFG_LSP_CAN15_SR_CFG_U32                                             (0x00000003UL) /*None*/
#define CAN15_SR_CFG_LSP_CAN15_SR_CFG_SHIFT_U32                                       (0U)

#define LSP_DEBUG_SEL_LSP_DEBUG_SEL_U32                                               (0xFFFFFFFFUL) /*None*/
#define LSP_DEBUG_SEL_LSP_DEBUG_SEL_SHIFT_U32                                         (0U)

#define CANFD_CTRL_LSP_TS_COUNTER_EN_U32                                              (0x00000008UL) /*None*/
#define CANFD_CTRL_LSP_TS_COUNTER_EN_SHIFT_U32                                        (3U)
#define CANFD_CTRL_LSP_TS_COUNTER_SEL_U32                                             (0x00000004UL) /*None*/
#define CANFD_CTRL_LSP_TS_COUNTER_SEL_SHIFT_U32                                       (2U)
#define CANFD_CTRL_LSP_TS_TIMESTAMP_GET_REQ_U32                                       (0x00000002UL) /*None*/
#define CANFD_CTRL_LSP_TS_TIMESTAMP_GET_REQ_SHIFT_U32                                 (1U)
#define CANFD_CTRL_LSP_TS_TIMESTAMP_GET_ACK_U32                                       (0x00000001UL) /*None*/
#define CANFD_CTRL_LSP_TS_TIMESTAMP_GET_ACK_SHIFT_U32                                 (0U)

#define CANFD_TIMESTAMP_VALUE_H_LSP_TS_TIMESTAMP_GET_VALUE_H_U32                      (0xFFFFFFFFUL) /*None*/
#define CANFD_TIMESTAMP_VALUE_H_LSP_TS_TIMESTAMP_GET_VALUE_H_SHIFT_U32                (0U)

#define CANFD_TIMESTAMP_VALUE_L_LSP_TS_TIMESTAMP_GET_VALUE_L_U32                      (0xFFFFFFFFUL) /*None*/
#define CANFD_TIMESTAMP_VALUE_L_LSP_TS_TIMESTAMP_GET_VALUE_L_SHIFT_U32                (0U)

#define CANFD_TIMESTAMP_COUNTER_LSP_TS_COUNTER_GET_VALUE_U32                          (0xFFFFFFFFUL) /*None*/
#define CANFD_TIMESTAMP_COUNTER_LSP_TS_COUNTER_GET_VALUE_SHIFT_U32                    (0U)

#define LSP_FREQ_CHECK_EN_CANFD0_FRQ_CHK_EN_U32                                       (0x00100000UL) /*None*/
#define LSP_FREQ_CHECK_EN_CANFD0_FRQ_CHK_EN_SHIFT_U32                                 (20U)
#define LSP_FREQ_CHECK_EN_CANFD1_FRQ_CHK_EN_U32                                       (0x00080000UL) /*None*/
#define LSP_FREQ_CHECK_EN_CANFD1_FRQ_CHK_EN_SHIFT_U32                                 (19U)
#define LSP_FREQ_CHECK_EN_CANFD2_FRQ_CHK_EN_U32                                       (0x00040000UL) /*None*/
#define LSP_FREQ_CHECK_EN_CANFD2_FRQ_CHK_EN_SHIFT_U32                                 (18U)
#define LSP_FREQ_CHECK_EN_CANFD3_FRQ_CHK_EN_U32                                       (0x00020000UL) /*None*/
#define LSP_FREQ_CHECK_EN_CANFD3_FRQ_CHK_EN_SHIFT_U32                                 (17U)
#define LSP_FREQ_CHECK_EN_CANFD4_FRQ_CHK_EN_U32                                       (0x00010000UL) /*None*/
#define LSP_FREQ_CHECK_EN_CANFD4_FRQ_CHK_EN_SHIFT_U32                                 (16U)
#define LSP_FREQ_CHECK_EN_CANFD5_FRQ_CHK_EN_U32                                       (0x00008000UL) /*None*/
#define LSP_FREQ_CHECK_EN_CANFD5_FRQ_CHK_EN_SHIFT_U32                                 (15U)
#define LSP_FREQ_CHECK_EN_CANFD6_FRQ_CHK_EN_U32                                       (0x00004000UL) /*None*/
#define LSP_FREQ_CHECK_EN_CANFD6_FRQ_CHK_EN_SHIFT_U32                                 (14U)
#define LSP_FREQ_CHECK_EN_CANFD7_FRQ_CHK_EN_U32                                       (0x00002000UL) /*None*/
#define LSP_FREQ_CHECK_EN_CANFD7_FRQ_CHK_EN_SHIFT_U32                                 (13U)
#define LSP_FREQ_CHECK_EN_CANFD8_FRQ_CHK_EN_U32                                       (0x00001000UL) /*None*/
#define LSP_FREQ_CHECK_EN_CANFD8_FRQ_CHK_EN_SHIFT_U32                                 (12U)
#define LSP_FREQ_CHECK_EN_CANFD9_FRQ_CHK_EN_U32                                       (0x00000800UL) /*None*/
#define LSP_FREQ_CHECK_EN_CANFD9_FRQ_CHK_EN_SHIFT_U32                                 (11U)
#define LSP_FREQ_CHECK_EN_CANFD10_FRQ_CHK_EN_U32                                      (0x00000400UL) /*None*/
#define LSP_FREQ_CHECK_EN_CANFD10_FRQ_CHK_EN_SHIFT_U32                                (10U)
#define LSP_FREQ_CHECK_EN_CANFD11_FRQ_CHK_EN_U32                                      (0x00000200UL) /*None*/
#define LSP_FREQ_CHECK_EN_CANFD11_FRQ_CHK_EN_SHIFT_U32                                (9U)
#define LSP_FREQ_CHECK_EN_CANFD12_FRQ_CHK_EN_U32                                      (0x00000100UL) /*None*/
#define LSP_FREQ_CHECK_EN_CANFD12_FRQ_CHK_EN_SHIFT_U32                                (8U)
#define LSP_FREQ_CHECK_EN_CANFD13_FRQ_CHK_EN_U32                                      (0x00000080UL) /*None*/
#define LSP_FREQ_CHECK_EN_CANFD13_FRQ_CHK_EN_SHIFT_U32                                (7U)
#define LSP_FREQ_CHECK_EN_CANFD14_FRQ_CHK_EN_U32                                      (0x00000040UL) /*None*/
#define LSP_FREQ_CHECK_EN_CANFD14_FRQ_CHK_EN_SHIFT_U32                                (6U)
#define LSP_FREQ_CHECK_EN_CANFD15_FRQ_CHK_EN_U32                                      (0x00000020UL) /*None*/
#define LSP_FREQ_CHECK_EN_CANFD15_FRQ_CHK_EN_SHIFT_U32                                (5U)
#define LSP_FREQ_CHECK_EN_LSP_WCLK_FREQ_CHECK_EN_U32                                  (0x00000010UL) /*None*/
#define LSP_FREQ_CHECK_EN_LSP_WCLK_FREQ_CHECK_EN_SHIFT_U32                            (4U)
#define LSP_FREQ_CHECK_EN_LSP_PCLK_FREQ_CHECK_EN_U32                                  (0x00000008UL) /*None*/
#define LSP_FREQ_CHECK_EN_LSP_PCLK_FREQ_CHECK_EN_SHIFT_U32                            (3U)
#define LSP_FREQ_CHECK_EN_RAY_WCLK_FREQ_CHECK_EN_U32                                  (0x00000004UL) /*None*/
#define LSP_FREQ_CHECK_EN_RAY_WCLK_FREQ_CHECK_EN_SHIFT_U32                            (2U)
#define LSP_FREQ_CHECK_EN_LIN_PCLK_FREQ_CHECK_EN_U32                                  (0x00000002UL) /*None*/
#define LSP_FREQ_CHECK_EN_LIN_PCLK_FREQ_CHECK_EN_SHIFT_U32                            (1U)
#define LSP_FREQ_CHECK_EN_LIN_WCLK_FREQ_CHECK_EN_U32                                  (0x00000001UL) /*None*/
#define LSP_FREQ_CHECK_EN_LIN_WCLK_FREQ_CHECK_EN_SHIFT_U32                            (0U)

#define LSP_RREQ_INTR0_CANFD0_HIGHCLK_INTR_CLR_U32                                    (0x80000000UL) /*None*/
#define LSP_RREQ_INTR0_CANFD0_HIGHCLK_INTR_CLR_SHIFT_U32                              (31U)
#define LSP_RREQ_INTR0_CANFD0_HIGHCLK_INTR_MASK_U32                                   (0x40000000UL) /*None*/
#define LSP_RREQ_INTR0_CANFD0_HIGHCLK_INTR_MASK_SHIFT_U32                             (30U)
#define LSP_RREQ_INTR0_CANFD0_HIGHCLK_INTR_STATE_U32                                  (0x20000000UL) /*None*/
#define LSP_RREQ_INTR0_CANFD0_HIGHCLK_INTR_STATE_SHIFT_U32                            (29U)
#define LSP_RREQ_INTR0_CANFD0_HIGHCLK_INTR_U32                                        (0x10000000UL) /*None*/
#define LSP_RREQ_INTR0_CANFD0_HIGHCLK_INTR_SHIFT_U32                                  (28U)
#define LSP_RREQ_INTR0_CANFD1_HIGHCLK_INTR_CLR_U32                                    (0x08000000UL) /*None*/
#define LSP_RREQ_INTR0_CANFD1_HIGHCLK_INTR_CLR_SHIFT_U32                              (27U)
#define LSP_RREQ_INTR0_CANFD1_HIGHCLK_INTR_MASK_U32                                   (0x04000000UL) /*None*/
#define LSP_RREQ_INTR0_CANFD1_HIGHCLK_INTR_MASK_SHIFT_U32                             (26U)
#define LSP_RREQ_INTR0_CANFD1_HIGHCLK_INTR_STATE_U32                                  (0x02000000UL) /*None*/
#define LSP_RREQ_INTR0_CANFD1_HIGHCLK_INTR_STATE_SHIFT_U32                            (25U)
#define LSP_RREQ_INTR0_CANFD1_HIGHCLK_INTR_U32                                        (0x01000000UL) /*None*/
#define LSP_RREQ_INTR0_CANFD1_HIGHCLK_INTR_SHIFT_U32                                  (24U)
#define LSP_RREQ_INTR0_CANFD2_HIGHCLK_INTR_CLR_U32                                    (0x00800000UL) /*None*/
#define LSP_RREQ_INTR0_CANFD2_HIGHCLK_INTR_CLR_SHIFT_U32                              (23U)
#define LSP_RREQ_INTR0_CANFD2_HIGHCLK_INTR_MASK_U32                                   (0x00400000UL) /*None*/
#define LSP_RREQ_INTR0_CANFD2_HIGHCLK_INTR_MASK_SHIFT_U32                             (22U)
#define LSP_RREQ_INTR0_CANFD2_HIGHCLK_INTR_STATE_U32                                  (0x00200000UL) /*None*/
#define LSP_RREQ_INTR0_CANFD2_HIGHCLK_INTR_STATE_SHIFT_U32                            (21U)
#define LSP_RREQ_INTR0_CANFD2_HIGHCLK_INTR_U32                                        (0x00100000UL) /*None*/
#define LSP_RREQ_INTR0_CANFD2_HIGHCLK_INTR_SHIFT_U32                                  (20U)
#define LSP_RREQ_INTR0_LSP_WCLK_FREQ_HIGHCLK_INTR_CLR_U32                             (0x00080000UL) /*None*/
#define LSP_RREQ_INTR0_LSP_WCLK_FREQ_HIGHCLK_INTR_CLR_SHIFT_U32                       (19U)
#define LSP_RREQ_INTR0_LSP_WCLK_FREQ_HIGHCLK_INTR_MASK_U32                            (0x00040000UL) /*None*/
#define LSP_RREQ_INTR0_LSP_WCLK_FREQ_HIGHCLK_INTR_MASK_SHIFT_U32                      (18U)
#define LSP_RREQ_INTR0_LSP_WCLK_FREQ_HIGHCLK_INTR_STATE_U32                           (0x00020000UL) /*None*/
#define LSP_RREQ_INTR0_LSP_WCLK_FREQ_HIGHCLK_INTR_STATE_SHIFT_U32                     (17U)
#define LSP_RREQ_INTR0_LSP_WCLK_FREQ_HIGHCLK_INTR_U32                                 (0x00010000UL) /*None*/
#define LSP_RREQ_INTR0_LSP_WCLK_FREQ_HIGHCLK_INTR_SHIFT_U32                           (16U)
#define LSP_RREQ_INTR0_LSP_PCLK_FREQ_HIGHCLK_INTR_CLR_U32                             (0x00008000UL) /*None*/
#define LSP_RREQ_INTR0_LSP_PCLK_FREQ_HIGHCLK_INTR_CLR_SHIFT_U32                       (15U)
#define LSP_RREQ_INTR0_LSP_PCLK_FREQ_HIGHCLK_INTR_MASK_U32                            (0x00004000UL) /*None*/
#define LSP_RREQ_INTR0_LSP_PCLK_FREQ_HIGHCLK_INTR_MASK_SHIFT_U32                      (14U)
#define LSP_RREQ_INTR0_LSP_PCLK_FREQ_HIGHCLK_INTR_STATE_U32                           (0x00002000UL) /*None*/
#define LSP_RREQ_INTR0_LSP_PCLK_FREQ_HIGHCLK_INTR_STATE_SHIFT_U32                     (13U)
#define LSP_RREQ_INTR0_LSP_PCLK_FREQ_HIGHCLK_INTR_U32                                 (0x00001000UL) /*None*/
#define LSP_RREQ_INTR0_LSP_PCLK_FREQ_HIGHCLK_INTR_SHIFT_U32                           (12U)
#define LSP_RREQ_INTR0_RAY_WCLK_FREQ_HIGHCLK_INTR_CLR_U32                             (0x00000800UL) /*None*/
#define LSP_RREQ_INTR0_RAY_WCLK_FREQ_HIGHCLK_INTR_CLR_SHIFT_U32                       (11U)
#define LSP_RREQ_INTR0_RAY_WCLK_FREQ_HIGHCLK_INTR_MASK_U32                            (0x00000400UL) /*None*/
#define LSP_RREQ_INTR0_RAY_WCLK_FREQ_HIGHCLK_INTR_MASK_SHIFT_U32                      (10U)
#define LSP_RREQ_INTR0_RAY_WCLK_FREQ_HIGHCLK_INTR_STATE_U32                           (0x00000200UL) /*None*/
#define LSP_RREQ_INTR0_RAY_WCLK_FREQ_HIGHCLK_INTR_STATE_SHIFT_U32                     (9U)
#define LSP_RREQ_INTR0_RAY_WCLK_FREQ_HIGHCLK_INTR_U32                                 (0x00000100UL) /*None*/
#define LSP_RREQ_INTR0_RAY_WCLK_FREQ_HIGHCLK_INTR_SHIFT_U32                           (8U)
#define LSP_RREQ_INTR0_LIN_PCLK_FREQ_HIGHCLK_INTR_CLR_U32                             (0x00000080UL) /*None*/
#define LSP_RREQ_INTR0_LIN_PCLK_FREQ_HIGHCLK_INTR_CLR_SHIFT_U32                       (7U)
#define LSP_RREQ_INTR0_LIN_PCLK_FREQ_HIGHCLK_INTR_MASK_U32                            (0x00000040UL) /*None*/
#define LSP_RREQ_INTR0_LIN_PCLK_FREQ_HIGHCLK_INTR_MASK_SHIFT_U32                      (6U)
#define LSP_RREQ_INTR0_LIN_PCLK_FREQ_HIGHCLK_INTR_STATE_U32                           (0x00000020UL) /*None*/
#define LSP_RREQ_INTR0_LIN_PCLK_FREQ_HIGHCLK_INTR_STATE_SHIFT_U32                     (5U)
#define LSP_RREQ_INTR0_LIN_PCLK_FREQ_HIGHCLK_INTR_U32                                 (0x00000010UL) /*None*/
#define LSP_RREQ_INTR0_LIN_PCLK_FREQ_HIGHCLK_INTR_SHIFT_U32                           (4U)
#define LSP_RREQ_INTR0_LIN_WCLK_FREQ_HIGHCLK_INTR_CLR_U32                             (0x00000008UL) /*None*/
#define LSP_RREQ_INTR0_LIN_WCLK_FREQ_HIGHCLK_INTR_CLR_SHIFT_U32                       (3U)
#define LSP_RREQ_INTR0_LIN_WCLK_FREQ_HIGHCLK_INTR_MASK_U32                            (0x00000004UL) /*None*/
#define LSP_RREQ_INTR0_LIN_WCLK_FREQ_HIGHCLK_INTR_MASK_SHIFT_U32                      (2U)
#define LSP_RREQ_INTR0_LIN_WCLK_FREQ_HIGHCLK_INTR_STATE_U32                           (0x00000002UL) /*None*/
#define LSP_RREQ_INTR0_LIN_WCLK_FREQ_HIGHCLK_INTR_STATE_SHIFT_U32                     (1U)
#define LSP_RREQ_INTR0_LIN_WCLK_FREQ_HIGHCLK_INTR_U32                                 (0x00000001UL) /*None*/
#define LSP_RREQ_INTR0_LIN_WCLK_FREQ_HIGHCLK_INTR_SHIFT_U32                           (0U)

#define LSP_RREQ_INTR1_CANFD3_HIGHCLK_INTR_CLR_U32                                    (0x80000000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD3_HIGHCLK_INTR_CLR_SHIFT_U32                              (31U)
#define LSP_RREQ_INTR1_CANFD3_HIGHCLK_INTR_MASK_U32                                   (0x40000000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD3_HIGHCLK_INTR_MASK_SHIFT_U32                             (30U)
#define LSP_RREQ_INTR1_CANFD3_HIGHCLK_INTR_STATE_U32                                  (0x20000000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD3_HIGHCLK_INTR_STATE_SHIFT_U32                            (29U)
#define LSP_RREQ_INTR1_CANFD3_HIGHCLK_INTR_U32                                        (0x10000000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD3_HIGHCLK_INTR_SHIFT_U32                                  (28U)
#define LSP_RREQ_INTR1_CANFD4_HIGHCLK_INTR_CLR_U32                                    (0x08000000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD4_HIGHCLK_INTR_CLR_SHIFT_U32                              (27U)
#define LSP_RREQ_INTR1_CANFD4_HIGHCLK_INTR_MASK_U32                                   (0x04000000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD4_HIGHCLK_INTR_MASK_SHIFT_U32                             (26U)
#define LSP_RREQ_INTR1_CANFD4_HIGHCLK_INTR_STATE_U32                                  (0x02000000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD4_HIGHCLK_INTR_STATE_SHIFT_U32                            (25U)
#define LSP_RREQ_INTR1_CANFD4_HIGHCLK_INTR_U32                                        (0x01000000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD4_HIGHCLK_INTR_SHIFT_U32                                  (24U)
#define LSP_RREQ_INTR1_CANFD5_HIGHCLK_INTR_CLR_U32                                    (0x00800000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD5_HIGHCLK_INTR_CLR_SHIFT_U32                              (23U)
#define LSP_RREQ_INTR1_CANFD5_HIGHCLK_INTR_MASK_U32                                   (0x00400000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD5_HIGHCLK_INTR_MASK_SHIFT_U32                             (22U)
#define LSP_RREQ_INTR1_CANFD5_HIGHCLK_INTR_STATE_U32                                  (0x00200000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD5_HIGHCLK_INTR_STATE_SHIFT_U32                            (21U)
#define LSP_RREQ_INTR1_CANFD5_HIGHCLK_INTR_U32                                        (0x00100000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD5_HIGHCLK_INTR_SHIFT_U32                                  (20U)
#define LSP_RREQ_INTR1_CANFD6_HIGHCLK_INTR_CLR_U32                                    (0x00080000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD6_HIGHCLK_INTR_CLR_SHIFT_U32                              (19U)
#define LSP_RREQ_INTR1_CANFD6_HIGHCLK_INTR_MASK_U32                                   (0x00040000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD6_HIGHCLK_INTR_MASK_SHIFT_U32                             (18U)
#define LSP_RREQ_INTR1_CANFD6_HIGHCLK_INTR_STATE_U32                                  (0x00020000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD6_HIGHCLK_INTR_STATE_SHIFT_U32                            (17U)
#define LSP_RREQ_INTR1_CANFD6_HIGHCLK_INTR_U32                                        (0x00010000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD6_HIGHCLK_INTR_SHIFT_U32                                  (16U)
#define LSP_RREQ_INTR1_CANFD7_HIGHCLK_INTR_CLR_U32                                    (0x00008000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD7_HIGHCLK_INTR_CLR_SHIFT_U32                              (15U)
#define LSP_RREQ_INTR1_CANFD7_HIGHCLK_INTR_MASK_U32                                   (0x00004000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD7_HIGHCLK_INTR_MASK_SHIFT_U32                             (14U)
#define LSP_RREQ_INTR1_CANFD7_HIGHCLK_INTR_STATE_U32                                  (0x00002000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD7_HIGHCLK_INTR_STATE_SHIFT_U32                            (13U)
#define LSP_RREQ_INTR1_CANFD7_HIGHCLK_INTR_U32                                        (0x00001000UL) /*None*/
#define LSP_RREQ_INTR1_CANFD7_HIGHCLK_INTR_SHIFT_U32                                  (12U)
#define LSP_RREQ_INTR1_CANFD8_HIGHCLK_INTR_CLR_U32                                    (0x00000800UL) /*None*/
#define LSP_RREQ_INTR1_CANFD8_HIGHCLK_INTR_CLR_SHIFT_U32                              (11U)
#define LSP_RREQ_INTR1_CANFD8_HIGHCLK_INTR_MASK_U32                                   (0x00000400UL) /*None*/
#define LSP_RREQ_INTR1_CANFD8_HIGHCLK_INTR_MASK_SHIFT_U32                             (10U)
#define LSP_RREQ_INTR1_CANFD8_HIGHCLK_INTR_STATE_U32                                  (0x00000200UL) /*None*/
#define LSP_RREQ_INTR1_CANFD8_HIGHCLK_INTR_STATE_SHIFT_U32                            (9U)
#define LSP_RREQ_INTR1_CANFD8_HIGHCLK_INTR_U32                                        (0x00000100UL) /*None*/
#define LSP_RREQ_INTR1_CANFD8_HIGHCLK_INTR_SHIFT_U32                                  (8U)
#define LSP_RREQ_INTR1_CANFD9_HIGHCLK_INTR_CLR_U32                                    (0x00000080UL) /*None*/
#define LSP_RREQ_INTR1_CANFD9_HIGHCLK_INTR_CLR_SHIFT_U32                              (7U)
#define LSP_RREQ_INTR1_CANFD9_HIGHCLK_INTR_MASK_U32                                   (0x00000040UL) /*None*/
#define LSP_RREQ_INTR1_CANFD9_HIGHCLK_INTR_MASK_SHIFT_U32                             (6U)
#define LSP_RREQ_INTR1_CANFD9_HIGHCLK_INTR_STATE_U32                                  (0x00000020UL) /*None*/
#define LSP_RREQ_INTR1_CANFD9_HIGHCLK_INTR_STATE_SHIFT_U32                            (5U)
#define LSP_RREQ_INTR1_CANFD9_HIGHCLK_INTR_U32                                        (0x00000010UL) /*None*/
#define LSP_RREQ_INTR1_CANFD9_HIGHCLK_INTR_SHIFT_U32                                  (4U)
#define LSP_RREQ_INTR1_CANFD10_HIGHCLK_INTR_CLR_U32                                   (0x00000008UL) /*None*/
#define LSP_RREQ_INTR1_CANFD10_HIGHCLK_INTR_CLR_SHIFT_U32                             (3U)
#define LSP_RREQ_INTR1_CANFD10_HIGHCLK_INTR_MASK_U32                                  (0x00000004UL) /*None*/
#define LSP_RREQ_INTR1_CANFD10_HIGHCLK_INTR_MASK_SHIFT_U32                            (2U)
#define LSP_RREQ_INTR1_CANFD10_HIGHCLK_INTR_STATE_U32                                 (0x00000002UL) /*None*/
#define LSP_RREQ_INTR1_CANFD10_HIGHCLK_INTR_STATE_SHIFT_U32                           (1U)
#define LSP_RREQ_INTR1_CANFD10_HIGHCLK_INTR_U32                                       (0x00000001UL) /*None*/
#define LSP_RREQ_INTR1_CANFD10_HIGHCLK_INTR_SHIFT_U32                                 (0U)

#define LSP_RREQ_INTR2_CANFD11_HIGHCLK_INTR_CLR_U32                                   (0x00080000UL) /*None*/
#define LSP_RREQ_INTR2_CANFD11_HIGHCLK_INTR_CLR_SHIFT_U32                             (19U)
#define LSP_RREQ_INTR2_CANFD11_HIGHCLK_INTR_MASK_U32                                  (0x00040000UL) /*None*/
#define LSP_RREQ_INTR2_CANFD11_HIGHCLK_INTR_MASK_SHIFT_U32                            (18U)
#define LSP_RREQ_INTR2_CANFD11_HIGHCLK_INTR_STATE_U32                                 (0x00020000UL) /*None*/
#define LSP_RREQ_INTR2_CANFD11_HIGHCLK_INTR_STATE_SHIFT_U32                           (17U)
#define LSP_RREQ_INTR2_CANFD11_HIGHCLK_INTR_U32                                       (0x00010000UL) /*None*/
#define LSP_RREQ_INTR2_CANFD11_HIGHCLK_INTR_SHIFT_U32                                 (16U)
#define LSP_RREQ_INTR2_CANFD12_HIGHCLK_INTR_CLR_U32                                   (0x00008000UL) /*None*/
#define LSP_RREQ_INTR2_CANFD12_HIGHCLK_INTR_CLR_SHIFT_U32                             (15U)
#define LSP_RREQ_INTR2_CANFD12_HIGHCLK_INTR_MASK_U32                                  (0x00004000UL) /*None*/
#define LSP_RREQ_INTR2_CANFD12_HIGHCLK_INTR_MASK_SHIFT_U32                            (14U)
#define LSP_RREQ_INTR2_CANFD12_HIGHCLK_INTR_STATE_U32                                 (0x00002000UL) /*None*/
#define LSP_RREQ_INTR2_CANFD12_HIGHCLK_INTR_STATE_SHIFT_U32                           (13U)
#define LSP_RREQ_INTR2_CANFD12_HIGHCLK_INTR_U32                                       (0x00001000UL) /*None*/
#define LSP_RREQ_INTR2_CANFD12_HIGHCLK_INTR_SHIFT_U32                                 (12U)
#define LSP_RREQ_INTR2_CANFD13_HIGHCLK_INTR_CLR_U32                                   (0x00000800UL) /*None*/
#define LSP_RREQ_INTR2_CANFD13_HIGHCLK_INTR_CLR_SHIFT_U32                             (11U)
#define LSP_RREQ_INTR2_CANFD13_HIGHCLK_INTR_MASK_U32                                  (0x00000400UL) /*None*/
#define LSP_RREQ_INTR2_CANFD13_HIGHCLK_INTR_MASK_SHIFT_U32                            (10U)
#define LSP_RREQ_INTR2_CANFD13_HIGHCLK_INTR_STATE_U32                                 (0x00000200UL) /*None*/
#define LSP_RREQ_INTR2_CANFD13_HIGHCLK_INTR_STATE_SHIFT_U32                           (9U)
#define LSP_RREQ_INTR2_CANFD13_HIGHCLK_INTR_U32                                       (0x00000100UL) /*None*/
#define LSP_RREQ_INTR2_CANFD13_HIGHCLK_INTR_SHIFT_U32                                 (8U)
#define LSP_RREQ_INTR2_CANFD14_HIGHCLK_INTR_CLR_U32                                   (0x00000080UL) /*None*/
#define LSP_RREQ_INTR2_CANFD14_HIGHCLK_INTR_CLR_SHIFT_U32                             (7U)
#define LSP_RREQ_INTR2_CANFD14_HIGHCLK_INTR_MASK_U32                                  (0x00000040UL) /*None*/
#define LSP_RREQ_INTR2_CANFD14_HIGHCLK_INTR_MASK_SHIFT_U32                            (6U)
#define LSP_RREQ_INTR2_CANFD14_HIGHCLK_INTR_STATE_U32                                 (0x00000020UL) /*None*/
#define LSP_RREQ_INTR2_CANFD14_HIGHCLK_INTR_STATE_SHIFT_U32                           (5U)
#define LSP_RREQ_INTR2_CANFD14_HIGHCLK_INTR_U32                                       (0x00000010UL) /*None*/
#define LSP_RREQ_INTR2_CANFD14_HIGHCLK_INTR_SHIFT_U32                                 (4U)
#define LSP_RREQ_INTR2_CANFD15_HIGHCLK_INTR_CLR_U32                                   (0x00000008UL) /*None*/
#define LSP_RREQ_INTR2_CANFD15_HIGHCLK_INTR_CLR_SHIFT_U32                             (3U)
#define LSP_RREQ_INTR2_CANFD15_HIGHCLK_INTR_MASK_U32                                  (0x00000004UL) /*None*/
#define LSP_RREQ_INTR2_CANFD15_HIGHCLK_INTR_MASK_SHIFT_U32                            (2U)
#define LSP_RREQ_INTR2_CANFD15_HIGHCLK_INTR_STATE_U32                                 (0x00000002UL) /*None*/
#define LSP_RREQ_INTR2_CANFD15_HIGHCLK_INTR_STATE_SHIFT_U32                           (1U)
#define LSP_RREQ_INTR2_CANFD15_HIGHCLK_INTR_U32                                       (0x00000001UL) /*None*/
#define LSP_RREQ_INTR2_CANFD15_HIGHCLK_INTR_SHIFT_U32                                 (0U)

#define LSP_WCLK_RREQ_REF_CLKCNT_LSP_WCLK_FREQ_REF_CLKCNT_BASE_U32                    (0x0000003FUL) /*None*/
#define LSP_WCLK_RREQ_REF_CLKCNT_LSP_WCLK_FREQ_REF_CLKCNT_BASE_SHIFT_U32              (0U)

#define LSP_WCLK_RREQ_HIGHCLKCNT_LSP_WCLK_FREQ_HIGHCLKCNT_BASE_U32                    (0x0000FFFFUL) /*None*/
#define LSP_WCLK_RREQ_HIGHCLKCNT_LSP_WCLK_FREQ_HIGHCLKCNT_BASE_SHIFT_U32              (0U)

#define LSP_WCLK_RREQ_THRESHOLD_LSP_WCLK_FREQ_THRESHOLD_U32                           (0x000000FFUL) /*None*/
#define LSP_WCLK_RREQ_THRESHOLD_LSP_WCLK_FREQ_THRESHOLD_SHIFT_U32                     (0U)

#define LSP_WCLK_RREQ_HIGHCLK_PPM_LSP_WCLK_FREQ_HIGHCLK_PPM_U32                       (0x000000FFUL) /*None*/
#define LSP_WCLK_RREQ_HIGHCLK_PPM_LSP_WCLK_FREQ_HIGHCLK_PPM_SHIFT_U32                 (0U)

#define LSP_PCLK_RREQ_REF_CLKCNT_LSP_PCLK_FREQ_REF_CLKCNT_BASE_U32                    (0x0000003FUL) /*None*/
#define LSP_PCLK_RREQ_REF_CLKCNT_LSP_PCLK_FREQ_REF_CLKCNT_BASE_SHIFT_U32              (0U)

#define LSP_PCLK_RREQ_HIGHCLKCNT_LSP_PCLK_FREQ_HIGHCLKCNT_BASE_U32                    (0x0000FFFFUL) /*None*/
#define LSP_PCLK_RREQ_HIGHCLKCNT_LSP_PCLK_FREQ_HIGHCLKCNT_BASE_SHIFT_U32              (0U)

#define LSP_PCLK_RREQ_THRESHOLD_LSP_PCLK_FREQ_THRESHOLD_U32                           (0x000000FFUL) /*None*/
#define LSP_PCLK_RREQ_THRESHOLD_LSP_PCLK_FREQ_THRESHOLD_SHIFT_U32                     (0U)

#define LSP_PCLK_RREQ_HIGHCLK_PPM_LSP_PCLK_FREQ_HIGHCLK_PPM_U32                       (0x000000FFUL) /*None*/
#define LSP_PCLK_RREQ_HIGHCLK_PPM_LSP_PCLK_FREQ_HIGHCLK_PPM_SHIFT_U32                 (0U)

#define RAY_WCLK_RREQ_REF_CLKCNT_RAY_WCLK_FREQ_REF_CLKCNT_BASE_U32                    (0x0000003FUL) /*None*/
#define RAY_WCLK_RREQ_REF_CLKCNT_RAY_WCLK_FREQ_REF_CLKCNT_BASE_SHIFT_U32              (0U)

#define RAY_WCLK_RREQ_HIGHCLKCNT_RAY_WCLK_FREQ_HIGHCLKCNT_BASE_U32                    (0x0000FFFFUL) /*None*/
#define RAY_WCLK_RREQ_HIGHCLKCNT_RAY_WCLK_FREQ_HIGHCLKCNT_BASE_SHIFT_U32              (0U)

#define RAY_WCLK_RREQ_THRESHOLD_RAY_WCLK_FREQ_THRESHOLD_U32                           (0x000000FFUL) /*None*/
#define RAY_WCLK_RREQ_THRESHOLD_RAY_WCLK_FREQ_THRESHOLD_SHIFT_U32                     (0U)

#define RAY_WCLK_RREQ_HIGHCLK_PPM_RAY_WCLK_FREQ_HIGHCLK_PPM_U32                       (0x000000FFUL) /*None*/
#define RAY_WCLK_RREQ_HIGHCLK_PPM_RAY_WCLK_FREQ_HIGHCLK_PPM_SHIFT_U32                 (0U)

#define LIN_WCLK_RREQ_REF_CLKCNT_LIN_WCLK_FREQ_REF_CLKCNT_BASE_U32                    (0x0000003FUL) /*None*/
#define LIN_WCLK_RREQ_REF_CLKCNT_LIN_WCLK_FREQ_REF_CLKCNT_BASE_SHIFT_U32              (0U)

#define LIN_WCLK_RREQ_HIGHCLKCNT_LIN_WCLK_FREQ_HIGHCLKCNT_BASE_U32                    (0x0000FFFFUL) /*None*/
#define LIN_WCLK_RREQ_HIGHCLKCNT_LIN_WCLK_FREQ_HIGHCLKCNT_BASE_SHIFT_U32              (0U)

#define LIN_WCLK_RREQ_THRESHOLD_LIN_WCLK_FREQ_THRESHOLD_U32                           (0x000000FFUL) /*None*/
#define LIN_WCLK_RREQ_THRESHOLD_LIN_WCLK_FREQ_THRESHOLD_SHIFT_U32                     (0U)

#define LIN_WCLK_RREQ_HIGHCLK_PPM_LIN_WCLK_FREQ_HIGHCLK_PPM_U32                       (0x000000FFUL) /*None*/
#define LIN_WCLK_RREQ_HIGHCLK_PPM_LIN_WCLK_FREQ_HIGHCLK_PPM_SHIFT_U32                 (0U)

#define LIN_PCLK_RREQ_REF_CLKCNT_LIN_PCLK_FREQ_REF_CLKCNT_BASE_U32                    (0x0000003FUL) /*None*/
#define LIN_PCLK_RREQ_REF_CLKCNT_LIN_PCLK_FREQ_REF_CLKCNT_BASE_SHIFT_U32              (0U)

#define LIN_PCLK_RREQ_HIGHCLKCNT_LIN_PCLK_FREQ_HIGHCLKCNT_BASE_U32                    (0x0000FFFFUL) /*None*/
#define LIN_PCLK_RREQ_HIGHCLKCNT_LIN_PCLK_FREQ_HIGHCLKCNT_BASE_SHIFT_U32              (0U)

#define LIN_PCLK_RREQ_THRESHOLD_LIN_PCLK_FREQ_THRESHOLD_U32                           (0x000000FFUL) /*None*/
#define LIN_PCLK_RREQ_THRESHOLD_LIN_PCLK_FREQ_THRESHOLD_SHIFT_U32                     (0U)

#define LIN_PCLK_RREQ_HIGHCLK_PPM_LIN_PCLK_FREQ_HIGHCLK_PPM_U32                       (0x000000FFUL) /*None*/
#define LIN_PCLK_RREQ_HIGHCLK_PPM_LIN_PCLK_FREQ_HIGHCLK_PPM_SHIFT_U32                 (0U)

#define CAN0_CLK_RREQ_REF_CLKCNT_CANFD0_REFCLKCNT_BASE_U32                            (0x0000003FUL) /*None*/
#define CAN0_CLK_RREQ_REF_CLKCNT_CANFD0_REFCLKCNT_BASE_SHIFT_U32                      (0U)

#define CAN0_CLK_RREQ_HIGHCLKCNT_CANFD0_HIGHCLKCNT_BASE_U32                           (0x0000FFFFUL) /*None*/
#define CAN0_CLK_RREQ_HIGHCLKCNT_CANFD0_HIGHCLKCNT_BASE_SHIFT_U32                     (0U)

#define CAN0_CLK_RREQ_THRESHOLD_CANFD0_FRQ_TH_U32                                     (0x000000FFUL) /*None*/
#define CAN0_CLK_RREQ_THRESHOLD_CANFD0_FRQ_TH_SHIFT_U32                               (0U)

#define CAN0_CLK_RREQ_HIGHCLK_PPM_CANFD0_HIGHCLK_PPM_U32                              (0x000000FFUL) /*None*/
#define CAN0_CLK_RREQ_HIGHCLK_PPM_CANFD0_HIGHCLK_PPM_SHIFT_U32                        (0U)

#define CAN1_CLK_RREQ_REF_CLKCNT_CANFD1_REFCLKCNT_BASE_U32                            (0x0000003FUL) /*None*/
#define CAN1_CLK_RREQ_REF_CLKCNT_CANFD1_REFCLKCNT_BASE_SHIFT_U32                      (0U)

#define CAN1_CLK_RREQ_HIGHCLKCNT_CANFD1_HIGHCLKCNT_BASE_U32                           (0x0000FFFFUL) /*None*/
#define CAN1_CLK_RREQ_HIGHCLKCNT_CANFD1_HIGHCLKCNT_BASE_SHIFT_U32                     (0U)

#define CAN1_CLK_RREQ_THRESHOLD_CANFD1_FRQ_TH_U32                                     (0x000000FFUL) /*None*/
#define CAN1_CLK_RREQ_THRESHOLD_CANFD1_FRQ_TH_SHIFT_U32                               (0U)

#define CAN1_CLK_RREQ_HIGHCLK_PPM_CANFD1_HIGHCLK_PPM_U32                              (0x000000FFUL) /*None*/
#define CAN1_CLK_RREQ_HIGHCLK_PPM_CANFD1_HIGHCLK_PPM_SHIFT_U32                        (0U)

#define CAN2_CLK_RREQ_REF_CLKCNT_CANFD2_REFCLKCNT_BASE_U32                            (0x0000003FUL) /*None*/
#define CAN2_CLK_RREQ_REF_CLKCNT_CANFD2_REFCLKCNT_BASE_SHIFT_U32                      (0U)

#define CAN2_CLK_RREQ_HIGHCLKCNT_CANFD2_HIGHCLKCNT_BASE_U32                           (0x0000FFFFUL) /*None*/
#define CAN2_CLK_RREQ_HIGHCLKCNT_CANFD2_HIGHCLKCNT_BASE_SHIFT_U32                     (0U)

#define CAN2_CLK_RREQ_THRESHOLD_CANFD2_FRQ_TH_U32                                     (0x000000FFUL) /*None*/
#define CAN2_CLK_RREQ_THRESHOLD_CANFD2_FRQ_TH_SHIFT_U32                               (0U)

#define CAN2_CLK_RREQ_HIGHCLK_PPM_CANFD2_HIGHCLK_PPM_U32                              (0x000000FFUL) /*None*/
#define CAN2_CLK_RREQ_HIGHCLK_PPM_CANFD2_HIGHCLK_PPM_SHIFT_U32                        (0U)

#define CAN3_CLK_RREQ_REF_CLKCNT_CANFD3_REFCLKCNT_BASE_U32                            (0x0000003FUL) /*None*/
#define CAN3_CLK_RREQ_REF_CLKCNT_CANFD3_REFCLKCNT_BASE_SHIFT_U32                      (0U)

#define CAN3_CLK_RREQ_HIGHCLKCNT_CANFD3_HIGHCLKCNT_BASE_U32                           (0x0000FFFFUL) /*None*/
#define CAN3_CLK_RREQ_HIGHCLKCNT_CANFD3_HIGHCLKCNT_BASE_SHIFT_U32                     (0U)

#define CAN3_CLK_RREQ_THRESHOLD_CANFD3_FRQ_TH_U32                                     (0x000000FFUL) /*None*/
#define CAN3_CLK_RREQ_THRESHOLD_CANFD3_FRQ_TH_SHIFT_U32                               (0U)

#define CAN3_CLK_RREQ_HIGHCLK_PPM_CANFD3_HIGHCLK_PPM_U32                              (0x000000FFUL) /*None*/
#define CAN3_CLK_RREQ_HIGHCLK_PPM_CANFD3_HIGHCLK_PPM_SHIFT_U32                        (0U)

#define CAN4_CLK_RREQ_REF_CLKCNT_CANFD4_REFCLKCNT_BASE_U32                            (0x0000003FUL) /*None*/
#define CAN4_CLK_RREQ_REF_CLKCNT_CANFD4_REFCLKCNT_BASE_SHIFT_U32                      (0U)

#define CAN4_CLK_RREQ_HIGHCLKCNT_CANFD4_HIGHCLKCNT_BASE_U32                           (0x0000FFFFUL) /*None*/
#define CAN4_CLK_RREQ_HIGHCLKCNT_CANFD4_HIGHCLKCNT_BASE_SHIFT_U32                     (0U)

#define CAN4_CLK_RREQ_THRESHOLD_CANFD4_FRQ_TH_U32                                     (0x000000FFUL) /*None*/
#define CAN4_CLK_RREQ_THRESHOLD_CANFD4_FRQ_TH_SHIFT_U32                               (0U)

#define CAN4_CLK_RREQ_HIGHCLK_PPM_CANFD4_HIGHCLK_PPM_U32                              (0x000000FFUL) /*None*/
#define CAN4_CLK_RREQ_HIGHCLK_PPM_CANFD4_HIGHCLK_PPM_SHIFT_U32                        (0U)

#define CAN5_CLK_RREQ_REF_CLKCNT_CANFD5_REFCLKCNT_BASE_U32                            (0x0000003FUL) /*None*/
#define CAN5_CLK_RREQ_REF_CLKCNT_CANFD5_REFCLKCNT_BASE_SHIFT_U32                      (0U)

#define CAN5_CLK_RREQ_HIGHCLKCNT_CANFD5_HIGHCLKCNT_BASE_U32                           (0x0000FFFFUL) /*None*/
#define CAN5_CLK_RREQ_HIGHCLKCNT_CANFD5_HIGHCLKCNT_BASE_SHIFT_U32                     (0U)

#define CAN5_CLK_RREQ_THRESHOLD_CANFD5_FRQ_TH_U32                                     (0x000000FFUL) /*None*/
#define CAN5_CLK_RREQ_THRESHOLD_CANFD5_FRQ_TH_SHIFT_U32                               (0U)

#define CAN5_CLK_RREQ_HIGHCLK_PPM_CANFD5_HIGHCLK_PPM_U32                              (0x000000FFUL) /*None*/
#define CAN5_CLK_RREQ_HIGHCLK_PPM_CANFD5_HIGHCLK_PPM_SHIFT_U32                        (0U)

#define CAN6_CLK_RREQ_REF_CLKCNT_CANFD6_REFCLKCNT_BASE_U32                            (0x0000003FUL) /*None*/
#define CAN6_CLK_RREQ_REF_CLKCNT_CANFD6_REFCLKCNT_BASE_SHIFT_U32                      (0U)

#define CAN6_CLK_RREQ_HIGHCLKCNT_CANFD6_HIGHCLKCNT_BASE_U32                           (0x0000FFFFUL) /*None*/
#define CAN6_CLK_RREQ_HIGHCLKCNT_CANFD6_HIGHCLKCNT_BASE_SHIFT_U32                     (0U)

#define CAN6_CLK_RREQ_THRESHOLD_CANFD6_FRQ_TH_U32                                     (0x000000FFUL) /*None*/
#define CAN6_CLK_RREQ_THRESHOLD_CANFD6_FRQ_TH_SHIFT_U32                               (0U)

#define CAN6_CLK_RREQ_HIGHCLK_PPM_CANFD6_HIGHCLK_PPM_U32                              (0x000000FFUL) /*None*/
#define CAN6_CLK_RREQ_HIGHCLK_PPM_CANFD6_HIGHCLK_PPM_SHIFT_U32                        (0U)

#define CAN7_CLK_RREQ_REF_CLKCNT_CANFD7_REFCLKCNT_BASE_U32                            (0x0000003FUL) /*None*/
#define CAN7_CLK_RREQ_REF_CLKCNT_CANFD7_REFCLKCNT_BASE_SHIFT_U32                      (0U)

#define CAN7_CLK_RREQ_HIGHCLKCNT_CANFD7_HIGHCLKCNT_BASE_U32                           (0x0000FFFFUL) /*None*/
#define CAN7_CLK_RREQ_HIGHCLKCNT_CANFD7_HIGHCLKCNT_BASE_SHIFT_U32                     (0U)

#define CAN7_CLK_RREQ_THRESHOLD_CANFD7_FRQ_TH_U32                                     (0x000000FFUL) /*None*/
#define CAN7_CLK_RREQ_THRESHOLD_CANFD7_FRQ_TH_SHIFT_U32                               (0U)

#define CAN7_CLK_RREQ_HIGHCLK_PPM_CANFD7_HIGHCLK_PPM_U32                              (0x000000FFUL) /*None*/
#define CAN7_CLK_RREQ_HIGHCLK_PPM_CANFD7_HIGHCLK_PPM_SHIFT_U32                        (0U)

#define CAN8_CLK_RREQ_REF_CLKCNT_CANFD8_REFCLKCNT_BASE_U32                            (0x0000003FUL) /*None*/
#define CAN8_CLK_RREQ_REF_CLKCNT_CANFD8_REFCLKCNT_BASE_SHIFT_U32                      (0U)

#define CAN8_CLK_RREQ_HIGHCLKCNT_CANFD8_HIGHCLKCNT_BASE_U32                           (0x0000FFFFUL) /*None*/
#define CAN8_CLK_RREQ_HIGHCLKCNT_CANFD8_HIGHCLKCNT_BASE_SHIFT_U32                     (0U)

#define CAN8_CLK_RREQ_THRESHOLD_CANFD8_FRQ_TH_U32                                     (0x000000FFUL) /*None*/
#define CAN8_CLK_RREQ_THRESHOLD_CANFD8_FRQ_TH_SHIFT_U32                               (0U)

#define CAN8_CLK_RREQ_HIGHCLK_PPM_CANFD8_HIGHCLK_PPM_U32                              (0x000000FFUL) /*None*/
#define CAN8_CLK_RREQ_HIGHCLK_PPM_CANFD8_HIGHCLK_PPM_SHIFT_U32                        (0U)

#define CAN9_CLK_RREQ_REF_CLKCNT_CANFD9_REFCLKCNT_BASE_U32                            (0x0000003FUL) /*None*/
#define CAN9_CLK_RREQ_REF_CLKCNT_CANFD9_REFCLKCNT_BASE_SHIFT_U32                      (0U)

#define CAN9_CLK_RREQ_HIGHCLKCNT_CANFD9_HIGHCLKCNT_BASE_U32                           (0x0000FFFFUL) /*None*/
#define CAN9_CLK_RREQ_HIGHCLKCNT_CANFD9_HIGHCLKCNT_BASE_SHIFT_U32                     (0U)

#define CAN9_CLK_RREQ_THRESHOLD_CANFD9_FRQ_TH_U32                                     (0x000000FFUL) /*None*/
#define CAN9_CLK_RREQ_THRESHOLD_CANFD9_FRQ_TH_SHIFT_U32                               (0U)

#define CAN9_CLK_RREQ_HIGHCLK_PPM_CANFD9_HIGHCLK_PPM_U32                              (0x000000FFUL) /*None*/
#define CAN9_CLK_RREQ_HIGHCLK_PPM_CANFD9_HIGHCLK_PPM_SHIFT_U32                        (0U)

#define CAN10_CLK_RREQ_REF_CLKCNT_CANFD10_REFCLKCNT_BASE_U32                          (0x0000003FUL) /*None*/
#define CAN10_CLK_RREQ_REF_CLKCNT_CANFD10_REFCLKCNT_BASE_SHIFT_U32                    (0U)

#define CAN10_CLK_RREQ_HIGHCLKCNT_CANFD10_HIGHCLKCNT_BASE_U32                         (0x0000FFFFUL) /*None*/
#define CAN10_CLK_RREQ_HIGHCLKCNT_CANFD10_HIGHCLKCNT_BASE_SHIFT_U32                   (0U)

#define CAN10_CLK_RREQ_THRESHOLD_CANFD10_FRQ_TH_U32                                   (0x000000FFUL) /*None*/
#define CAN10_CLK_RREQ_THRESHOLD_CANFD10_FRQ_TH_SHIFT_U32                             (0U)

#define CAN10_CLK_RREQ_HIGHCLK_PPM_CANFD10_HIGHCLK_PPM_U32                            (0x000000FFUL) /*None*/
#define CAN10_CLK_RREQ_HIGHCLK_PPM_CANFD10_HIGHCLK_PPM_SHIFT_U32                      (0U)

#define CAN11_CLK_RREQ_REF_CLKCNT_CANFD11_REFCLKCNT_BASE_U32                          (0x0000003FUL) /*None*/
#define CAN11_CLK_RREQ_REF_CLKCNT_CANFD11_REFCLKCNT_BASE_SHIFT_U32                    (0U)

#define CAN11_CLK_RREQ_HIGHCLKCNT_CANFD11_HIGHCLKCNT_BASE_U32                         (0x0000FFFFUL) /*None*/
#define CAN11_CLK_RREQ_HIGHCLKCNT_CANFD11_HIGHCLKCNT_BASE_SHIFT_U32                   (0U)

#define CAN11_CLK_RREQ_THRESHOLD_CANFD11_FRQ_TH_U32                                   (0x000000FFUL) /*None*/
#define CAN11_CLK_RREQ_THRESHOLD_CANFD11_FRQ_TH_SHIFT_U32                             (0U)

#define CAN11_CLK_RREQ_HIGHCLK_PPM_CANFD11_HIGHCLK_PPM_U32                            (0x000000FFUL) /*None*/
#define CAN11_CLK_RREQ_HIGHCLK_PPM_CANFD11_HIGHCLK_PPM_SHIFT_U32                      (0U)

#define CAN12_CLK_RREQ_REF_CLKCNT_CANFD12_REFCLKCNT_BASE_U32                          (0x0000003FUL) /*None*/
#define CAN12_CLK_RREQ_REF_CLKCNT_CANFD12_REFCLKCNT_BASE_SHIFT_U32                    (0U)

#define CAN12_CLK_RREQ_HIGHCLKCNT_CANFD12_HIGHCLKCNT_BASE_U32                         (0x0000FFFFUL) /*None*/
#define CAN12_CLK_RREQ_HIGHCLKCNT_CANFD12_HIGHCLKCNT_BASE_SHIFT_U32                   (0U)

#define CAN12_CLK_RREQ_THRESHOLD_CANFD12_FRQ_TH_U32                                   (0x000000FFUL) /*None*/
#define CAN12_CLK_RREQ_THRESHOLD_CANFD12_FRQ_TH_SHIFT_U32                             (0U)

#define CAN12_CLK_RREQ_HIGHCLK_PPM_CANFD12_HIGHCLK_PPM_U32                            (0x000000FFUL) /*None*/
#define CAN12_CLK_RREQ_HIGHCLK_PPM_CANFD12_HIGHCLK_PPM_SHIFT_U32                      (0U)

#define CAN13_CLK_RREQ_REF_CLKCNT_CANFD13_REFCLKCNT_BASE_U32                          (0x0000003FUL) /*None*/
#define CAN13_CLK_RREQ_REF_CLKCNT_CANFD13_REFCLKCNT_BASE_SHIFT_U32                    (0U)

#define CAN13_CLK_RREQ_HIGHCLKCNT_CANFD13_HIGHCLKCNT_BASE_U32                         (0x0000FFFFUL) /*None*/
#define CAN13_CLK_RREQ_HIGHCLKCNT_CANFD13_HIGHCLKCNT_BASE_SHIFT_U32                   (0U)

#define CAN13_CLK_RREQ_THRESHOLD_CANFD13_FRQ_TH_U32                                   (0x000000FFUL) /*None*/
#define CAN13_CLK_RREQ_THRESHOLD_CANFD13_FRQ_TH_SHIFT_U32                             (0U)

#define CAN13_CLK_RREQ_HIGHCLK_PPM_CANFD13_HIGHCLK_PPM_U32                            (0x000000FFUL) /*None*/
#define CAN13_CLK_RREQ_HIGHCLK_PPM_CANFD13_HIGHCLK_PPM_SHIFT_U32                      (0U)

#define CAN14_CLK_RREQ_REF_CLKCNT_CANFD14_REFCLKCNT_BASE_U32                          (0x0000003FUL) /*None*/
#define CAN14_CLK_RREQ_REF_CLKCNT_CANFD14_REFCLKCNT_BASE_SHIFT_U32                    (0U)

#define CAN14_CLK_RREQ_HIGHCLKCNT_CANFD14_HIGHCLKCNT_BASE_U32                         (0x0000FFFFUL) /*None*/
#define CAN14_CLK_RREQ_HIGHCLKCNT_CANFD14_HIGHCLKCNT_BASE_SHIFT_U32                   (0U)

#define CAN14_CLK_RREQ_THRESHOLD_CANFD14_FRQ_TH_U32                                   (0x000000FFUL) /*None*/
#define CAN14_CLK_RREQ_THRESHOLD_CANFD14_FRQ_TH_SHIFT_U32                             (0U)

#define CAN14_CLK_RREQ_HIGHCLK_PPM_CANFD14_HIGHCLK_PPM_U32                            (0x000000FFUL) /*None*/
#define CAN14_CLK_RREQ_HIGHCLK_PPM_CANFD14_HIGHCLK_PPM_SHIFT_U32                      (0U)

#define CAN15_CLK_RREQ_REF_CLKCNT_CANFD15_REFCLKCNT_BASE_U32                          (0x0000003FUL) /*None*/
#define CAN15_CLK_RREQ_REF_CLKCNT_CANFD15_REFCLKCNT_BASE_SHIFT_U32                    (0U)

#define CAN15_CLK_RREQ_HIGHCLKCNT_CANFD15_HIGHCLKCNT_BASE_U32                         (0x0000FFFFUL) /*None*/
#define CAN15_CLK_RREQ_HIGHCLKCNT_CANFD15_HIGHCLKCNT_BASE_SHIFT_U32                   (0U)

#define CAN15_CLK_RREQ_THRESHOLD_CANFD15_FRQ_TH_U32                                   (0x000000FFUL) /*None*/
#define CAN15_CLK_RREQ_THRESHOLD_CANFD15_FRQ_TH_SHIFT_U32                             (0U)

#define CAN15_CLK_RREQ_HIGHCLK_PPM_CANFD15_HIGHCLK_PPM_U32                            (0x000000FFUL) /*None*/
#define CAN15_CLK_RREQ_HIGHCLK_PPM_CANFD15_HIGHCLK_PPM_SHIFT_U32                      (0U)

#define FLEXCAN_PARITY_IRQ_FLEXCAN_PARITY_ERR_IRQ_U32                                 (0x0000FFFFUL) /*None*/
#define FLEXCAN_PARITY_IRQ_FLEXCAN_PARITY_ERR_IRQ_SHIFT_U32                           (0U)

#define LIN_PARITY_STATUS0_LIN0_PRDATA_PARITY_ERR_INJECT_U32                          (0x08000000UL) /*None*/
#define LIN_PARITY_STATUS0_LIN0_PRDATA_PARITY_ERR_INJECT_SHIFT_U32                    (27U)
#define LIN_PARITY_STATUS0_LIN0_PADDR_PARITY_IRQ_U32                                  (0x04000000UL) /*None*/
#define LIN_PARITY_STATUS0_LIN0_PADDR_PARITY_IRQ_SHIFT_U32                            (26U)
#define LIN_PARITY_STATUS0_LIN0_PWDATA_PARITY_IRQ_U32                                 (0x02000000UL) /*None*/
#define LIN_PARITY_STATUS0_LIN0_PWDATA_PARITY_IRQ_SHIFT_U32                           (25U)
#define LIN_PARITY_STATUS0_LIN0_PADDR_PARITY_IRQ_CLR_U32                              (0x01000000UL) /*None*/
#define LIN_PARITY_STATUS0_LIN0_PADDR_PARITY_IRQ_CLR_SHIFT_U32                        (24U)
#define LIN_PARITY_STATUS0_LIN0_PWDATA_PARITY_IRQ_CLR_U32                             (0x00800000UL) /*None*/
#define LIN_PARITY_STATUS0_LIN0_PWDATA_PARITY_IRQ_CLR_SHIFT_U32                       (23U)
#define LIN_PARITY_STATUS0_LIN0_PADDR_PARITY_IRQ_MASK_U32                             (0x00400000UL) /*None*/
#define LIN_PARITY_STATUS0_LIN0_PADDR_PARITY_IRQ_MASK_SHIFT_U32                       (22U)
#define LIN_PARITY_STATUS0_LIN0_PWDATA_PARITY_IRQ_MASK_U32                            (0x00200000UL) /*None*/
#define LIN_PARITY_STATUS0_LIN0_PWDATA_PARITY_IRQ_MASK_SHIFT_U32                      (21U)
#define LIN_PARITY_STATUS0_LIN1_PADDR_PARITY_IRQ_U32                                  (0x00100000UL) /*None*/
#define LIN_PARITY_STATUS0_LIN1_PADDR_PARITY_IRQ_SHIFT_U32                            (20U)
#define LIN_PARITY_STATUS0_LIN1_PWDATA_PARITY_IRQ_U32                                 (0x00080000UL) /*None*/
#define LIN_PARITY_STATUS0_LIN1_PWDATA_PARITY_IRQ_SHIFT_U32                           (19U)
#define LIN_PARITY_STATUS0_LIN1_PRDATA_PARITY_ERR_INJECT_U32                          (0x00040000UL) /*None*/
#define LIN_PARITY_STATUS0_LIN1_PRDATA_PARITY_ERR_INJECT_SHIFT_U32                    (18U)
#define LIN_PARITY_STATUS0_LIN1_PADDR_PARITY_IRQ_CLR_U32                              (0x00020000UL) /*None*/
#define LIN_PARITY_STATUS0_LIN1_PADDR_PARITY_IRQ_CLR_SHIFT_U32                        (17U)
#define LIN_PARITY_STATUS0_LIN1_PWDATA_PARITY_IRQ_CLR_U32                             (0x00010000UL) /*None*/
#define LIN_PARITY_STATUS0_LIN1_PWDATA_PARITY_IRQ_CLR_SHIFT_U32                       (16U)
#define LIN_PARITY_STATUS0_LIN1_PADDR_PARITY_IRQ_MASK_U32                             (0x00008000UL) /*None*/
#define LIN_PARITY_STATUS0_LIN1_PADDR_PARITY_IRQ_MASK_SHIFT_U32                       (15U)
#define LIN_PARITY_STATUS0_LIN1_PWDATA_PARITY_IRQ_MASK_U32                            (0x00004000UL) /*None*/
#define LIN_PARITY_STATUS0_LIN1_PWDATA_PARITY_IRQ_MASK_SHIFT_U32                      (14U)
#define LIN_PARITY_STATUS0_LIN2_PADDR_PARITY_IRQ_U32                                  (0x00002000UL) /*None*/
#define LIN_PARITY_STATUS0_LIN2_PADDR_PARITY_IRQ_SHIFT_U32                            (13U)
#define LIN_PARITY_STATUS0_LIN2_PWDATA_PARITY_IRQ_U32                                 (0x00001000UL) /*None*/
#define LIN_PARITY_STATUS0_LIN2_PWDATA_PARITY_IRQ_SHIFT_U32                           (12U)
#define LIN_PARITY_STATUS0_LIN2_PRDATA_PARITY_ERR_INJECT_U32                          (0x00000800UL) /*None*/
#define LIN_PARITY_STATUS0_LIN2_PRDATA_PARITY_ERR_INJECT_SHIFT_U32                    (11U)
#define LIN_PARITY_STATUS0_LIN2_PADDR_PARITY_IRQ_CLR_U32                              (0x00000400UL) /*None*/
#define LIN_PARITY_STATUS0_LIN2_PADDR_PARITY_IRQ_CLR_SHIFT_U32                        (10U)
#define LIN_PARITY_STATUS0_LIN2_PWDATA_PARITY_IRQ_CLR_U32                             (0x00000200UL) /*None*/
#define LIN_PARITY_STATUS0_LIN2_PWDATA_PARITY_IRQ_CLR_SHIFT_U32                       (9U)
#define LIN_PARITY_STATUS0_LIN2_PADDR_PARITY_IRQ_MASK_U32                             (0x00000100UL) /*None*/
#define LIN_PARITY_STATUS0_LIN2_PADDR_PARITY_IRQ_MASK_SHIFT_U32                       (8U)
#define LIN_PARITY_STATUS0_LIN2_PWDATA_PARITY_IRQ_MASK_U32                            (0x00000080UL) /*None*/
#define LIN_PARITY_STATUS0_LIN2_PWDATA_PARITY_IRQ_MASK_SHIFT_U32                      (7U)
#define LIN_PARITY_STATUS0_LIN3_PADDR_PARITY_IRQ_U32                                  (0x00000040UL) /*None*/
#define LIN_PARITY_STATUS0_LIN3_PADDR_PARITY_IRQ_SHIFT_U32                            (6U)
#define LIN_PARITY_STATUS0_LIN3_PWDATA_PARITY_IRQ_U32                                 (0x00000020UL) /*None*/
#define LIN_PARITY_STATUS0_LIN3_PWDATA_PARITY_IRQ_SHIFT_U32                           (5U)
#define LIN_PARITY_STATUS0_LIN3_PRDATA_PARITY_ERR_INJECT_U32                          (0x00000010UL) /*None*/
#define LIN_PARITY_STATUS0_LIN3_PRDATA_PARITY_ERR_INJECT_SHIFT_U32                    (4U)
#define LIN_PARITY_STATUS0_LIN3_PADDR_PARITY_IRQ_CLR_U32                              (0x00000008UL) /*None*/
#define LIN_PARITY_STATUS0_LIN3_PADDR_PARITY_IRQ_CLR_SHIFT_U32                        (3U)
#define LIN_PARITY_STATUS0_LIN3_PWDATA_PARITY_IRQ_CLR_U32                             (0x00000004UL) /*None*/
#define LIN_PARITY_STATUS0_LIN3_PWDATA_PARITY_IRQ_CLR_SHIFT_U32                       (2U)
#define LIN_PARITY_STATUS0_LIN3_PADDR_PARITY_IRQ_MASK_U32                             (0x00000002UL) /*None*/
#define LIN_PARITY_STATUS0_LIN3_PADDR_PARITY_IRQ_MASK_SHIFT_U32                       (1U)
#define LIN_PARITY_STATUS0_LIN3_PWDATA_PARITY_IRQ_MASK_U32                            (0x00000001UL) /*None*/
#define LIN_PARITY_STATUS0_LIN3_PWDATA_PARITY_IRQ_MASK_SHIFT_U32                      (0U)

#define LIN_PARITY_STATUS1_LIN4_PRDATA_PARITY_ERR_INJECT_U32                          (0x00002000UL) /*None*/
#define LIN_PARITY_STATUS1_LIN4_PRDATA_PARITY_ERR_INJECT_SHIFT_U32                    (13U)
#define LIN_PARITY_STATUS1_LIN4_PADDR_PARITY_IRQ_U32                                  (0x00001000UL) /*None*/
#define LIN_PARITY_STATUS1_LIN4_PADDR_PARITY_IRQ_SHIFT_U32                            (12U)
#define LIN_PARITY_STATUS1_LIN4_PWDATA_PARITY_IRQ_U32                                 (0x00000800UL) /*None*/
#define LIN_PARITY_STATUS1_LIN4_PWDATA_PARITY_IRQ_SHIFT_U32                           (11U)
#define LIN_PARITY_STATUS1_LIN4_PADDR_PARITY_IRQ_CLR_U32                              (0x00000400UL) /*None*/
#define LIN_PARITY_STATUS1_LIN4_PADDR_PARITY_IRQ_CLR_SHIFT_U32                        (10U)
#define LIN_PARITY_STATUS1_LIN4_PWDATA_PARITY_IRQ_CLR_U32                             (0x00000200UL) /*None*/
#define LIN_PARITY_STATUS1_LIN4_PWDATA_PARITY_IRQ_CLR_SHIFT_U32                       (9U)
#define LIN_PARITY_STATUS1_LIN4_PADDR_PARITY_IRQ_MASK_U32                             (0x00000100UL) /*None*/
#define LIN_PARITY_STATUS1_LIN4_PADDR_PARITY_IRQ_MASK_SHIFT_U32                       (8U)
#define LIN_PARITY_STATUS1_LIN4_PWDATA_PARITY_IRQ_MASK_U32                            (0x00000080UL) /*None*/
#define LIN_PARITY_STATUS1_LIN4_PWDATA_PARITY_IRQ_MASK_SHIFT_U32                      (7U)
#define LIN_PARITY_STATUS1_LIN5_PADDR_PARITY_IRQ_U32                                  (0x00000040UL) /*None*/
#define LIN_PARITY_STATUS1_LIN5_PADDR_PARITY_IRQ_SHIFT_U32                            (6U)
#define LIN_PARITY_STATUS1_LIN5_PWDATA_PARITY_IRQ_U32                                 (0x00000020UL) /*None*/
#define LIN_PARITY_STATUS1_LIN5_PWDATA_PARITY_IRQ_SHIFT_U32                           (5U)
#define LIN_PARITY_STATUS1_LIN5_PRDATA_PARITY_ERR_INJECT_U32                          (0x00000010UL) /*None*/
#define LIN_PARITY_STATUS1_LIN5_PRDATA_PARITY_ERR_INJECT_SHIFT_U32                    (4U)
#define LIN_PARITY_STATUS1_LIN5_PADDR_PARITY_IRQ_CLR_U32                              (0x00000008UL) /*None*/
#define LIN_PARITY_STATUS1_LIN5_PADDR_PARITY_IRQ_CLR_SHIFT_U32                        (3U)
#define LIN_PARITY_STATUS1_LIN5_PWDATA_PARITY_IRQ_CLR_U32                             (0x00000004UL) /*None*/
#define LIN_PARITY_STATUS1_LIN5_PWDATA_PARITY_IRQ_CLR_SHIFT_U32                       (2U)
#define LIN_PARITY_STATUS1_LIN5_PADDR_PARITY_IRQ_MASK_U32                             (0x00000002UL) /*None*/
#define LIN_PARITY_STATUS1_LIN5_PADDR_PARITY_IRQ_MASK_SHIFT_U32                       (1U)
#define LIN_PARITY_STATUS1_LIN5_PWDATA_PARITY_IRQ_MASK_U32                            (0x00000001UL) /*None*/
#define LIN_PARITY_STATUS1_LIN5_PWDATA_PARITY_IRQ_MASK_SHIFT_U32                      (0U)

#define LIN_IPG_STOP_LIN_IPG_STOP_U32                                                 (0x00000FC0UL) /*None*/
#define LIN_IPG_STOP_LIN_IPG_STOP_SHIFT_U32                                           (6U)
#define LIN_IPG_STOP_LIN_IPG_STOP_ACK_U32                                             (0x0000003FUL) /*None*/
#define LIN_IPG_STOP_LIN_IPG_STOP_ACK_SHIFT_U32                                       (0U)

#define RSV0_RSV0_U32                                                                 (0xFFFFFFFFUL) /*None*/
#define RSV0_RSV0_SHIFT_U32                                                           (0U)

#define RSV1_RSV1_U32                                                                 (0xFFFFFFFFUL) /*None*/
#define RSV1_RSV1_SHIFT_U32                                                           (0U)

#endif